Polyphase Filter Phase Correction With Selective Delay Paths

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Solution Overview

Problem

Conventional polyphase filters with multiple paths and adjustable delay circuits suffer from significant phase errors due to mismatches between paths.

Innovation Solution

A polyphase filter design with only the second and third paths equipped with adjustable delay circuits, coupled with a quadrature phase detector to control these circuits and generate clock signals with ideal phases, while the first and fourth paths lack adjustable delay circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If adjustable delay circuits are added to all paths to control phase, then phase control precision is improved, but device complexity and mismatch errors increase

Engineering Contradiction:
Improvephase control precisionVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The polyphase filter is divided into four paths (first, second, third, and fourth paths), with adjustable delay circuits selectively applied only to the second and third paths. This segmentation allows phase control where needed while avoiding unnecessary complexity in paths where phase adjustment is not required.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different paths are treated differently regarding phase control. The second and third paths receive adjustable delay circuits for precise phase control, while the first and fourth paths use fixed delay structures. This local differentiation optimizes the balance between phase control precision and device complexity.

Inventive Principle:
Principle #3Local quality

2Measurement precision

If adjustable delay circuits are added to all paths, then phase control capability is improved, but power consumption increases

Engineering Contradiction:
Improvephase control capabilityVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The filter structure is segmented into paths with different delay control requirements. Only the second and third paths contain adjustable delay circuits that consume power for phase control, while the first and fourth paths use power-efficient fixed delay structures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Phase control is applied partially rather than universally - only to the extent necessary for the second and third paths. This partial action reduces overall power consumption while maintaining adequate phase control capability where needed.

Inventive Principle:
Principle #16Partial or excessive action

3Adaptability or versatility

If adjustable delay circuits are added to all paths, then phase adjustment range is improved, but mismatch errors increase

Engineering Contradiction:
Improvephase adjustment rangeVSAvoidmismatch errors
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The four paths are segmented into two groups: paths with adjustable delay circuits (second and third) and paths without (first and fourth). This reduces the total number of adjustable components, thereby reducing cumulative mismatch errors while maintaining adequate phase adjustment range through the quadrature phase detector.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A quadrature phase detector is introduced to provide feedback for controlling the adjustable delay circuits in the second and third paths. This feedback mechanism ensures accurate phase control with fewer adjustable components, reducing mismatch errors compared to having multiple independent adjustable delay circuits in all paths.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11811413B2Poly phase filter with phase error enhance technique
Publication Date: 2023.11.07 MEDIATEK INC
  • US11811413B2 patent drawing
  • US11811413B2 patent drawing

AI summary

The present invention provides a filtering circuit comprising a poly phase filter and a quadrature phase detector. The poly phase filter comprises a first path, a second path, a third path and a fourth path. The first path is configured to receive a first input signal to generate a first clock signal. The second path comprising a first adjustable delay circuit is configured to receive the first input signal to generate a second clock signal. The third path comprising a second adjustable delay circuit is configured to receive a second input signal to generate a third clock signal. The fourth path is configured to receive the second input signal to generate a fourth clock signal. The quadrature phase detector is configured to detect phases of these clock signals to generate control signals to control the first adjustable delay circuit and the second adjustable delay circuit.