Parallel DSP Demodulation via Polyphase Filters
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current digital signal processing in communication systems, particularly in modems, faces limitations due to the speed constraints of field programmable gate arrays (FPGAs) and digital signal processors (DSPs), which restrict the maximum bit rate for filtering and other processing functions, necessitating the use of application-specific integrated circuits (ASICs) for high-speed operations.
Innovation Solution
The implementation of a demodulator with parallel block polyphase filters and digital down-conversion, allowing for concurrent processing of multiple signal channels at a reduced sample rate, enabling the use of FPGAs and DSPs for high-speed signal processing and accommodating various signal formats and modulation technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs and DSPs are used for digital signal processing, then flexibility and programmability are improved, but processing speed deteriorates compared to ASICs
Solution Approach 1:
The filter is divided into multiple parallel sub-filters (polyphase components) that process different phases of the input signal simultaneously. This segmentation allows the system to achieve high processing speeds by distributing the computational load across multiple parallel processing elements within the FPGA or DSP, effectively resolving the speed limitation while maintaining programmability.
Solution Approach 2:
The invention transitions from sequential single-channel processing to parallel multi-channel processing by decomposing the filter into polyphase components. This dimensional change from time-domain sequential processing to parallel channel processing enables the system to achieve ASIC-level processing speeds while retaining the flexibility of FPGAs and DSPs.
2Productivity
If sampling rate is increased to handle high data rates, then bandwidth is improved, but processing complexity increases
Solution Approach 1:
By segmenting the high-rate filtering operation into multiple lower-rate parallel sub-filter operations, the system can handle high data rates without proportionally increasing the complexity of each processing element. Each sub-filter operates at a reduced sampling rate, simplifying the computational requirements while maintaining overall high throughput through parallelism.
Solution Approach 2:
The invention changes the operational parameters by operating multiple sub-filters at a lower sampling rate rather than a single filter at a high sampling rate. This parameter transformation reduces the computational complexity of each processing element while achieving the same effective processing rate through parallel operation.
Data Source
AI summary
A demodulator, suitable for use in a communication system and in a modem, has a block polyphase circuit with circuit blocks for different signal processing functions, particularly filtering, delay, and frequency conversion. The circuit blocks are arranged for parallel processing of different portions of an input sequence of signals. Signals of the input sequence to be filtered are divided among the blocks by a demultiplexer for processing at a clock frequency lower than a clock frequency of the input signal sequence. Signals outputted by groups of the circuit blocks are summed to produce an output signal of the group. Output signals of all of the groups are multiplexed to provide an output signal sequence such that the repetition frequency of the outputted signals may be higher, lower, or equal to that of the input signal sequence. This enables use of programmable circuitry operative at reduced clock rates.