Poly-Phase FIR Filter Timing for Jitter-Robust Sigma-Delta ADCs
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Solution Overview
Problem
Conventional sigma delta analog to digital converters face issues with jitter in the timing of the 2× clock signal, leading to sensitivity to process and voltage variations, resulting in yield loss due to improper operation at manufacturing corners.
Innovation Solution
A novel sigma delta converter architecture that integrates analog and digital sections, using a delay element to synchronize bit streams with a phase-delayed clock, reducing jitter and ensuring robust timing interface between sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 2× clock signal is used to synchronize bit streams in conventional sigma delta converters, then timing alignment between analog and digital sections is achieved, but jitter in the clock signal causes sensitivity to process and voltage variations
Solution Approach 1:
The patent implements dynamic phase adjustment of the clock signal through a delay element that can be tuned to optimize timing alignment. The system dynamically adapts the clock phase to compensate for process and voltage variations, transforming a static timing problem into a dynamically adjustable solution that maintains reliability across manufacturing corners.
2Device complexity
If conventional separate analog and digital sections are used, then design simplicity is maintained, but timing interface issues arise due to jitter sensitivity
Solution Approach 1:
The patent merges the analog and digital sections into a more tightly integrated architecture where the delay element serves as a shared timing reference between sections. This integration reduces the timing interface problems by creating a unified timing domain, sacrificing some structural simplicity for significantly improved timing reliability.
3Ease of manufacture
If manufacturing corners are tested with conventional timing, then production testing is simplified, but yield loss occurs due to improper operation at extreme conditions
Solution Approach 1:
The patent performs preliminary timing calibration through the adjustable delay element during initialization or setup, preparing the system to handle extreme operating conditions before actual production testing. This preliminary action ensures that the converter is pre-configured to operate correctly at manufacturing corners, preventing yield loss without complicating the actual production testing process.
Data Source
AI summary
A sigma delta analog to digital converter includes a clock operating at a conversion clock rate and first and second conversion paths. The first path includes a first sigma delta modulator configured to produce from an input analog signal a first bit stream at the clock rate, and a first digital filter configured to decimate the first bit stream. The second conversion path has a second sigma delta modulator configured to produce from the input analog signal a second bit stream separate from the first bit stream at the clock rate, and a second digital filter configured to decimate the second bit stream.