Polyphase FIR Filtering of Unary Data Without High-Rate Conversion
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Solution Overview
Problem
Existing digital filters face challenges in efficiently processing unary coded data due to high throughput requirements and precision demands, particularly when non-unity gain values are used, leading to increased circuit complexity and power consumption.
Innovation Solution
A circuit comprising K polyphase finite impulse response filter circuits, each processing a bit of the unary data word with single-bit precision, followed by gain adjustment and summation to generate filtered output, allowing for direct filtering of unary data without the need for high-rate unary to binary conversion, reducing computational complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high throughput processing is implemented for unary coded data, then processing speed is improved, but circuit complexity increases
Solution Approach 1:
The filter is divided into multiple polyphase filter circuits (K circuits for K-bit unary data), each processing individual bits in parallel. This segmentation enables high throughput processing while keeping each individual circuit simple, resolving the contradiction between processing speed and circuit complexity.
Solution Approach 2:
The patent transitions from sequential processing to parallel processing by utilizing the bit-position dimension of unary coded data. Each bit position is processed independently by a dedicated polyphase filter circuit, achieving high throughput without proportionally increasing overall circuit complexity.
2Measurement precision
If high precision filtering is applied to unary coded data, then filtering accuracy is improved, but power consumption increases
Solution Approach 1:
Different polyphase filter circuits use different gain values tailored to their specific bit position requirements. This local optimization allows accurate filtering while minimizing power consumption by using minimal necessary precision for each individual circuit rather than uniformly high precision across all circuits.
Solution Approach 2:
The patent applies different gain parameters to different polyphase filter circuits based on their position in the unary coded data. By adjusting these parameters locally rather than using uniform high precision throughout, the system achieves accurate filtering with reduced overall power consumption.
3Measurement precision
If non-unity gain values are used in polyphase filter circuits, then filtering accuracy is improved, but circuit complexity increases
Solution Approach 1:
The gain adjustment function is segmented across multiple independent polyphase filter circuits, each with its own gain stage. This allows non-unity gain values to be applied locally to improve filtering accuracy without requiring a complex centralized gain control mechanism, thus managing circuit complexity effectively.
4Productivity
If unary to binary conversion is performed at high rate, then processing throughput is improved, but computational complexity increases
Solution Approach 1:
Instead of converting unary to binary first and then filtering, the patent inverts the conventional approach by filtering the unary coded data directly in its native format. This eliminates the computationally complex unary-to-binary conversion step while maintaining high processing throughput through parallel polyphase filtering.
Solution Approach 2:
The patent extracts and eliminates the unnecessary unary-to-binary conversion step from the processing pipeline. By filtering unary data directly, the system removes the computational complexity of conversion while preserving the essential filtering function, achieving high throughput with reduced computational burden.
Data Source
AI summary
Individual bits of a K bit unary data word, wherein K is greater than one, are applied to K polyphase finite impulse response filter circuits. Each polyphase finite impulse response filter circuit receives a different bit and operates with a single bit precision to generate from each received bit a filtered output data word. A gain adjustment is applied by a gain stage circuit to each filtered output data word to generate a corresponding gain adjusted output data word. The gain adjusted output data words from the gain stage circuits are summed to generate an output data word. The unary data word may be output from a source such as a data encoder or a quantizer.