Poly-Phase Interleaved DAC Architecture for Lower-Noise RF Output
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Solution Overview
Problem
High-sample rate, high-linearity digital-to-analog converters (DACs) used in RF radio transmit paths face challenges with large size, complexity, and high power consumption due to stringent linearity and noise requirements, particularly in over-sampled architectures where the digital circuitry must operate at elevated speeds, leading to supply-induced noise and non-linearity issues.
Innovation Solution
The DAC architecture decomposes the delta-sigma modulator into a parallel poly-phase block-filter running at a lower rate, with 1-hot-of-N encoding and analog multiplexing, allowing direct combination of parallel digital outputs in the analog domain to simplify high-speed digital-analog timing interfaces and minimize signal-dependent supply noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If over-sampled architecture is used to reduce DAC complexity, then the number of physical bits required is reduced, but the data rate must be increased
Solution Approach 1:
The patent divides the high-speed data path into multiple parallel lower-speed data paths. Specifically, the 16-bit high-speed input is segmented into multiple 4-bit or 8-bit channels that operate at lower rates, allowing the use of simpler, lower-speed DAC elements while maintaining the overall high data rate through parallel processing
Solution Approach 2:
The patent transitions from a single high-speed serial data path to a multi-dimensional parallel architecture. By spatially distributing the data across multiple parallel channels (adding a spatial dimension), the system achieves high effective data rate without requiring each individual channel to operate at the full high speed, thus reducing complexity in each channel
2Speed
If high-speed digital circuitry is used to achieve high sample rates, then the signal bandwidth is increased, but supply induced-noise increases causing spurious emissions
Solution Approach 1:
The patent segments the high-speed switching operation into multiple lower-speed parallel operations. Each parallel channel switches at a lower rate, reducing the instantaneous current demand and associated supply-induced noise in each channel. The parallel architecture distributes the switching activity across multiple channels, preventing concentration of noise in a single high-speed path
Solution Approach 2:
The patent employs periodic interleaving of multiple lower-speed data streams to synthesize the high-speed output. By periodically alternating between parallel channels in a controlled manner, the system achieves high effective sample rate while each individual channel operates periodically at a lower rate, reducing supply noise while maintaining overall performance
3Ease of manufacture
If parallel digital outputs are combined in digital domain, then the data processing is simplified, but the timing interface complexity increases
Solution Approach 1:
The patent introduces an analog multiplexer as an intermediary device that performs the combining function in the analog domain rather than digitally. This analog multiplexer receives parallel digital control signals and switches between corresponding analog inputs, effectively acting as a mediator that translates digital selection signals into analog switching actions, thereby simplifying the digital interface requirements
Solution Approach 2:
The patent replaces complex digital timing and synchronization circuitry with an analog multiplexing approach. Instead of using digital logic to combine parallel data streams with complex timing requirements, the system uses an analog multiplexer controlled by simpler digital select signals, substituting mechanical/electrical switching for complex digital timing operations
Data Source
AI summary
A method and apparatus for interleaving high-speed, delta-sigma based over-sampled DACs. A delta-sigma modulator is decomposed into a parallel poly-phase block-filter running at a lower rate. The generated parallel digital data is then fed directly to the analog DAC output stage where it is directly combined to form the full-rate signal using a 1-hot-of-N output stage. By using a poly-phase implementation, the complexity of the high-speed parallel digital-analog timing interface is simplified, along with the timing requirements of the delta-sigma modulator which normally would have to run at the full-oversampled rate. The 1-hot-of-N signal encoding is directly generated from the parallel delta-sigma modulator, and efficiently encodes the data in such a way to minimize signal-dependent supply noise. The architecture disclosed is advantageous for the practical implementation of high-speed over-sampled DACs, such as those used in stringent wireless applications.