Polyphase NCO Phase Interpolation Beyond Host Clock Limits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current numerically controlled oscillators (NCOs) are limited by their clock rate, restricting the output frequency to half the clock rate due to the Nyquist limit, which cannot keep pace with the increasing speeds of digital-to-analog converters and field programmable gate arrays (FPGAs), preventing them from utilizing higher speed DACs effectively.
Innovation Solution
A polyphase numerically controlled oscillator system that uses a single phase accumulator and phase interpolator to generate multiple phase angles, allowing the clock rate to exceed that of the host circuitry, enabling frequencies beyond the traditional Nyquist limit by interpolating phase angles between the current and next anticipated phase, and distributing these to multiple phase-to-amplitude converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a traditional numerically controlled oscillator is used with a single phase accumulator and phase to amplitude converter, then the device complexity is reduced, but the clock rate is limited and cannot exceed the host circuitry clock rate due to the Nyquist limit
Solution Approach 1:
The phase to amplitude conversion function is segmented into multiple parallel converters (first, second, third, and fourth phase to amplitude converters), each handling a specific phase range. This segmentation allows the system to operate at higher clock rates by distributing the conversion workload across multiple parallel units rather than requiring a single high-speed converter.
Solution Approach 2:
The invention introduces a time dimension to the phase to amplitude conversion process by using multiple converters operating in parallel at different phase offsets. This dimensional approach allows the system to achieve effective oversampling and exceed the traditional Nyquist limit by combining outputs from multiple converters that are timed to cover the full phase cycle.
2Productivity
If the clock rate is increased to match faster DACs and FPGAs, then the productivity and speed are improved, but the output frequency is restricted to half the clock rate due to the Nyquist limit
Solution Approach 1:
Multiple phase to amplitude converters are pre-configured with different phase offsets (e.g., 0, π/2, π, 3π/2) and operate in parallel to pre-compute amplitude values for different portions of the phase cycle. This preliminary action allows the system to effectively generate frequencies beyond the traditional Nyquist limit by combining these pre-computed values at the appropriate times.
Solution Approach 2:
The outputs from multiple phase to amplitude converters are merged or combined to form the final output signal. This merging process integrates the contributions from all parallel converters, effectively synthesizing a waveform that achieves frequencies higher than what a single converter operating at the same clock rate could produce.
3Reliability
If a single phase accumulator and converter system is used, then the device complexity is low, but it cannot keep pace with the increasing speeds of digital-to-analog converters and field programmable gate arrays
Solution Approach 1:
The phase to amplitude conversion function is segmented into multiple parallel converters, each handling a specific phase range. This segmentation allows the system to operate at higher clock rates by distributing the conversion workload across multiple parallel units rather than requiring a single high-speed converter.
Solution Approach 2:
The polyphase NCO structure with multiple phase to amplitude converters provides multi-functionality by enabling the system to interface with various high-speed DACs and FPGAs. The parallel converter architecture can be configured to match different clock rates and frequency requirements, making the system universally compatible with different high-speed devices.
Data Source
AI summary
A polyphase numerically controlled oscillator is disclosed. An input signal is received at a phase accumulator. The phase accumulator provides a phase to a phase interpolator. The phase interpolator then provides a plurality of output phases. The plurality of output phases are provided to a plurality of phase to amplitude converters. Each of said plurality of phase to amplitude converters process one of said plurality of output phases.