Polyphase Pulse-Modulation Receiver for Low-Power RF Sampling
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Solution Overview
Problem
Forming satisfactory receiver circuitry in electronic devices with wireless communications capabilities is challenging due to issues with signal-to-noise ratio and excessive power consumption when receiving radio-frequency signals.
Innovation Solution
Implementing a polyphase pulse modulation-based receiver with a set of sample and hold circuits, pulse modulators, and time-to-digital converters, which convert radio-frequency signals into analog and digital codes using different phases of a clock signal, reducing the sampling rate with a pulse width modulation low pass filter and decimator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional receiver circuitry is used to receive radio-frequency signals, then the receiver can function, but it exhibits insufficient signal-to-noise ratio and consumes excessive power
Solution Approach 1:
The receiver is divided into multiple parallel sample-and-hold circuits, each processing a different phase of the RF signal. This segmentation allows the system to achieve high signal-to-noise ratio through coherent integration while keeping individual circuit segments low-power consuming
Solution Approach 2:
The receiver uses periodic sampling at multiple phases (0°, 90°, 180°, 270°) of the RF signal. By periodically sampling the signal at different phases and combining the results, the system achieves high signal-to-noise ratio while maintaining low power consumption through efficient use of sampling intervals
2Reliability
If high sampling rate is used to maintain signal quality, then signal-to-noise ratio is improved, but power consumption and chip area increase
Solution Approach 1:
Instead of continuous high-rate sampling, the system uses periodic sampling at four distinct phases within each RF cycle. This approach maintains signal quality through phase diversity while reducing the effective sampling rate requirement, thereby decreasing chip area
Solution Approach 2:
The system transitions from time-domain sampling to phase-domain processing by sampling at multiple phases (0°, 90°, 180°, 270°). This dimensional change allows equivalent signal quality to be achieved with lower sampling rates, reducing chip area requirements
3Use of energy by moving object
If polyphase pulse modulation is implemented, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The polyphase receiver is implemented as multiple identical sample-and-hold circuit segments operating in parallel, each handling a different phase. This modular segmentation makes the complex functionality manageable and implementable using standard circuit blocks
Solution Approach 2:
Each sample-and-hold circuit segment is designed to be universal and identical, performing the same function but on different phase inputs. This universality simplifies design and implementation while achieving the power consumption benefits of polyphase processing
Data Source
AI summary
An electronic device may include a receiver coupled to an antenna over a transmission line. The receiver may include a set of sample and hold circuits coupled in parallel between the transmission line and at least one pulse modulator. The pulse modulator(s) may be coupled between the sample and hold circuits and at least one time-to-digital converter (TDC). Each sample and hold circuit may be clocked using a different respective phase of a clock signal. During signal reception, the antenna may receive a radio-frequency signal. The sample and hold circuits may convert the radio-frequency signal into analog signals using the different phases of the clock signal. The pulse modulator(s) may convert voltages of the analog signals into pulse widths in at least one analog pulse width modulation (PWM) signal. The TDC(s) may convert the analog PWM signal(s) into digital codes.