Polyphase Quadrature Clock Generation With Lower Phase Noise

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Solution Overview

Problem

Existing quadrature signal generation methods for memory systems, such as DDR memory systems, face challenges including increased size, power consumption, and phase noise due to the use of divide-by-two circuits and dual oscillators, which can lead to high phase noise and tuning difficulties.

Innovation Solution

A quadrature signal generator that uses a filter bank, specifically a polyphase filter, to generate quadrature clock signals at the same frequency as the input clock signals, reducing the need for the clock generator's operating frequency to be twice that of the desired frequency, and incorporating a duty cycle and phase adjuster to optimize signal quality within a wideband frequency range of 2.5 GHz to 5 GHz.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a divide-by-two circuit with an oscillator at twice the desired frequency is used to generate quadrature signals, then quadrature clock signals can be generated, but phase noise increases and power consumption increases

Engineering Contradiction:
Improvequadrature signal generationVSAvoidphase noise
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the operating frequency parameter from twice the desired frequency to the same frequency, eliminating the need for frequency multiplication and subsequent division. This parameter change directly reduces phase noise while maintaining quadrature signal generation capability.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent extracts and removes the divide-by-two circuit from the system architecture. By using a filter bank instead, the harmful frequency division operation that introduces phase noise is eliminated while the quadrature signal generation function is preserved.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If a PLL with two coupled local oscillators is used to generate quadrature signals, then quadrature clock signals can be generated, but inductor area increases

Engineering Contradiction:
Improvequadrature signal generationVSAvoidinductor area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent removes the dual oscillator architecture and its associated large inductors from the system. By replacing it with a filter bank approach operating at the same frequency, the inductor area is dramatically reduced while maintaining quadrature signal generation.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the frequency generation and quadrature signal generation functions into a single stage operating at the desired frequency, eliminating the need for separate oscillators and reducing the overall inductor area requirement.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If the clock generator operates at twice the desired frequency to generate quadrature signals, then quadrature clock signals can be generated, but power consumption increases

Engineering Contradiction:
Improvequadrature signal generationVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent changes the operating frequency parameter from twice the desired frequency to the same frequency. This parameter change reduces the power consumption of the clock generator while maintaining the ability to generate quadrature signals through the filter bank.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces phase noise, power usage, and inductor area requirements, while maintaining high bandwidth capabilities, effectively addressing the limitations of previous methods by generating quadrature clock signals that meet the high bandwidth demands of modern memory systems without increasing the operating frequency of the clock generator.

Implementation Method 1

A quadrature signal generator that uses a filter bank, specifically a polyphase filter, to generate quadrature clock signals at the same frequency as the input clock signals

Methodology Applied
Scientific EffectFilter bank (polyphase filter): Filter (electronic)

Data Source

PatentUS10476660B1Quadrature signal generation
Publication Date: 2019.11.12 MICRON TECHNOLOGY INC
  • US10476660B1 patent drawing
  • US10476660B1 patent drawing
  • US10476660B1 patent drawing

AI summary

Apparatuses and methods for quadrature signal generation are provided. An example includes a quadrature signal generator. The quadrature signal generator is configured to generate, based on a received differential signal, a plurality of quadrature clock signals at a same frequency as that of the received differential signal. The quadrature signal generator is also configured to provide the plurality of quadrature clock signals to a memory system.