Polyphase Fractional Resampler Control for Parallel Fixed-Filter Processing
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Solution Overview
Problem
Existing fractional resampler systems face challenges in balancing flexibility, power efficiency, and area usage, with FPGA implementations consuming more power and ASIC implementations requiring large space to support arbitrary resampling ratios and high input sample rates.
Innovation Solution
A fractional resampling circuit using a single fixed coefficient filter with multiple phases that processes multiple input samples in parallel, allowing for simultaneous generation of output samples in a single clock cycle, while minimizing additional logic and avoiding the need for extra multipliers, thus achieving power savings and reduced area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a programmable filter with arbitrary P/Q support is used in FPGA implementation, then flexibility is improved, but power consumption increases
Solution Approach 1:
The patent implements a dynamically reconfigurable filter that can switch between fixed and programmable coefficient modes. The filter structure allows runtime reconfiguration where coefficient values can be updated through a coefficient register, enabling the system to adapt to different P/Q ratios while maintaining the hardware efficiency of fixed-coefficient implementations when arbitary flexibility is not needed.
2Use of energy by moving object
If fixed coefficient filters with fixed P/Q ratios are used in ASIC implementation, then power efficiency is improved, but area increases for high N values
Solution Approach 1:
The patent creates a universal filter structure that can function as both a fixed-coefficient filter and a programmable filter. By incorporating a coefficient register and control logic, the same hardware block can serve multiple purposes: operating in fixed-coefficient mode for power-efficient operation at specific P/Q ratios, and switching to programmable mode when arbitrary ratio support is required, thereby reducing the total area needed compared to having separate dedicated circuits for each mode.
3Productivity
If N sets of fixed coefficient filters are used to process N input samples in parallel, then productivity is improved, but area increases directly with N
Solution Approach 1:
The patent merges multiple filter instances into a single reconfigurable filter structure. Instead of implementing N separate fixed-coefficient filter sets to process N input samples in parallel, the invention uses one filter with dynamic coefficient updating capability. The filter processes samples sequentially with coefficient updates between processing stages, combining the functionality of multiple filters into a single area-efficient unit while maintaining overall productivity through pipelined operation.
Data Source
AI summary
Embodiments herein describe a hardened fractional resampler that includes a fixed filter that supports simultaneous processing of N input samples with minimal additional combinational logic and no additional multipliers. In one embodiment, the fractional resampler is implemented in an integrated circuit using hardened circuit. The embodiments below exploit a pattern in the order filter phases in fractional resampling systems (such as a SSR resampling system) to use filter phases in a single fixed filter to process multiple input samples in parallel, where these filter phases would have been unused in previous resampling systems.