Polysilicon Alignment Key Erosion in PMD CMP
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of contact holes in semiconductor devices using a pre-metal dielectric (PMD) layer can result in alignment key pattern erosion during the chemical mechanical polishing (CMP) process, making it difficult to recognize the alignment key pattern, which is crucial for subsequent processes.
Innovation Solution
Forming alignment key patterns composed of polysilicon in the active region of a semiconductor scribe lane or within the STI isolation region, which have a lower removal rate than the PMD layers, thereby reducing erosion and ensuring easy recognition during CMP processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a CMP process is performed on the PMD layer to polish the surface, then the surface flatness is improved, but the alignment key pattern is eroded and becomes difficult to recognize
Solution Approach 1:
The alignment key pattern is formed in advance on the etch-stop layer before the PMD layer is deposited and subjected to CMP. This preliminary formation ensures the pattern exists before the polishing process that would otherwise erode it
Solution Approach 2:
The etch-stop layer serves as an intermediary substrate that supports the alignment key pattern during the CMP process. By forming the pattern on this layer rather than directly on the PMD layer, the pattern is protected from CMP-induced erosion while still being visible for alignment purposes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively prevents alignment key pattern erosion and facilitates easy recognition of the alignment key, ensuring accurate and reliable semiconductor device formation by using polysilicon patterns that are less susceptible to CMP-induced erosion.
Implementation Method 1
chemical mechanical polishing (CMP) process
Implementation Method 2
have a lower removal rate than the PMD layers, thereby reducing erosion
Data Source
AI summary
A method of forming a pre-metal dielectric (PMD) layer of a semiconductor device using a chemical mechanical polishing (CMP) process which can be suitable for easily recognizing an alignment key. Such a method can reduce or otherwise eliminate alignment key erosion due to CMP by previously forming an alignment key pattern of polysilicon in an active region of a semiconductor scribe lane.