Polysilicon Layer Annealing for 3D NAND Oxidation Reliability
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Solution Overview
Problem
Three-dimensional semiconductor devices face issues such as high leakage, high thermal budget, low oxidation reliability, small crystal grain sizes, and peeling of conductive polysilicon layers due to radical oxidation processes during the fabrication of multilayer stacks for 3D vertical gate NAND devices.
Innovation Solution
A method involving a controlled temperature increase process, including in-situ annealing and oxidation, is used to form conductive polysilicon and insulating layers with larger crystal grains, reducing stress and improving layer integrity, which involves a first temperature increase from 200°C to 600°C followed by a second increase to 1050°C, with specific exposure times and gas mixtures to form stable layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If radical oxidation process is used to form insulating layers, then oxidation reliability is improved, but conductive polysilicon layers experience peeling and poly bubble formation
Solution Approach 1:
The patent applies preliminary annealing treatment to the conductive polysilicon layer before performing radical oxidation. This preliminary action reduces internal stress and improves the structural stability of the polysilicon layer, preventing peeling and poly bubble formation during the subsequent oxidation process while maintaining high oxidation reliability
Solution Approach 2:
The patent modifies process parameters by controlling the temperature profile and gas composition during oxidation. By optimizing these parameters, the patent achieves high oxidation reliability while minimizing damage to the conductive polysilicon layer structure
2Ease of manufacture
If conventional fabrication process is used, then manufacturing is simpler, but crystal grain sizes of conducting layers are small
Solution Approach 1:
The patent changes the temperature parameter during the annealing process, using a controlled temperature increase to promote crystal grain growth in the conductive polysilicon layer. This parameter change achieves larger crystal grain sizes while maintaining a relatively simple fabrication process
3Manufacturing precision
If high temperature processing is applied, then crystal grain size is improved, but thermal budget increases
Solution Approach 1:
The patent performs preliminary annealing at a moderate temperature before the main oxidation process. This preliminary action promotes initial crystal grain growth without requiring excessive temperature, thereby achieving good crystal grain size while controlling the overall thermal budget
Solution Approach 2:
The patent combines annealing and oxidation in a continuous process sequence, where the annealing phase prepares the polysilicon layer for subsequent oxidation. This continuous approach achieves crystal grain growth and oxidation reliability without requiring separate high-temperature processing steps that would increase thermal budget
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in semiconductor devices with low leakage, reduced thermal budget, high oxidation reliability, and large crystal grain sizes, preventing undesirable 'poly bubbles' and peeling, thereby enhancing the quality of the multilayer stacks.
Implementation Method 1
performing an in-situ annealing process to the conductive layer at the first increased temperature
Implementation Method 2
forming an insulating layer after performing the in-situ annealing process
Data Source
AI summary
Present example embodiments relate generally to methods of fabricating a semiconductor device, and semiconductor devices thereof, comprising providing a substrate, forming an insulating base layer on the substrate, and disposing a conductive layer on the insulating base layer at an initial temperature. The methods further comprise increasing the initial temperature at a first increase rate to a first increased temperature and performing an in-situ annealing process to the conductive layer at the first increased temperature. The methods further comprise increasing the first increased temperature at a second increase rate to a second increased temperature, and forming an insulating layer after performing the in-situ annealing process at the second increased temperature.