Polysilicon Cap Mitigates Metal Gate Dishing in CMP
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Solution Overview
Problem
Metal gate dishing occurs during the manufacturing of integrated circuits with high k-metal gate structures, particularly due to chemical mechanical polishing, leading to altered threshold voltage and inoperative PMOS devices, especially when MOS capacitors with large surface area metallization are polished.
Innovation Solution
The method involves distributing a polysilicon cap area larger than the combined surface areas of PMOS and NMOS device areas, which acts as a protective layer during chemical mechanical polishing to mitigate dishing effects, ensuring uniform polishing and reducing exposure of gate metal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing is performed on metal gates and MOS capacitors, then planarization is achieved, but dishing occurs leading to gate metal exposure and threshold voltage alteration
Solution Approach 1:
A polysilicon intermediary layer is introduced between the CMP process and the metal gate. This polysilicon layer serves as a sacrificial protective layer that absorbs the polishing action, preventing direct contact between the CMP slurry and the metal gate, thereby eliminating dishing while maintaining planarization benefits
Solution Approach 2:
The polysilicon cap is deposited onto the metal gate before the CMP process. This preliminary protective layer ensures that during subsequent polishing steps, the metal gate is already protected, preventing dishing and gate metal exposure before they can occur
2Ease of manufacture
If MOS capacitors with large surface area metallization are polished, then capacitor fabrication is completed, but dishing occurs due to large polished surface area
Solution Approach 1:
The polysilicon cap acts as an intermediary protective layer over the capacitor metallization during CMP. This layer distributes the polishing stress uniformly across the large capacitor surface area, preventing dishing while allowing the capacitor fabrication to proceed
3Reliability
If polysilicon cap area is increased to mitigate dishing, then protection against dishing is improved, but device area and complexity increase
Solution Approach 1:
The polysilicon cap structure serves multiple functions: it protects metal gates from dishing during CMP, provides a planar surface for subsequent processing steps, and can be selectively removed to expose underlying structures. This multi-functionality justifies the additional area by providing multiple benefits from a single structural element
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces metal gate dishing, maintaining the integrity of PMOS devices and preventing threshold voltage alterations by using the polysilicon cap area to distribute the polishing stress, thereby ensuring operational integrity.
Implementation Method 1
The substrate is then polished using a chemical mechanical polishing (CMP) system to planarize the metal at the top of the high k stack
Data Source
AI summary
A method and integrated circuit structure for mitigating metal gate dishing resulting from chemical mechanical polishing. The integrated circuit structure comprises a first area comprising at least one first type device; a second area comprising at least one second type device; a third area comprising at least one capacitor having an uppermost layer of polysilicon, where the capacitor area is greater than a sum of the first and second areas. The method utilizes the polysilicon of the capacitor to mitigate metal gate dishing of a metal gate of at least one device.