Polycrystalline Silicon Transistor Channel Orientation for Mobility
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Solution Overview
Problem
Polycrystalline silicon transistors in three-dimensional memory cell arrangements suffer from low carrier mobility, leading to insufficient current and degraded reading/programming speed due to small grain size, which is exacerbated by downscaling, resulting in reduced driving ability and increased chip surface area.
Innovation Solution
The semiconductor device employs a method where an amorphous silicon layer is crystallized to form a polycrystalline silicon layer with a sufficient grain size, reducing its thickness to maintain high channel mobility while increasing grain size, thereby enhancing the driving ability of selection transistors and improving memory cell operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polycrystalline silicon is used as the channel material in three-dimensional memory cell arrangements, then the transistor can be formed on insulating film or metal interconnect, but the carrier mobility is low leading to insufficient current and degraded reading/programming speed
Solution Approach 1:
The patent changes the crystal orientation parameter of the polycrystalline silicon channel from conventional orientations to <110> orientation, which fundamentally alters the carrier mobility characteristics and resolves the contradiction between manufacturability and performance
Solution Approach 2:
The patent uses a composite structure combining polycrystalline silicon with specific crystal orientation control, integrating the manufacturing advantages of polycrystalline silicon with the high mobility characteristics of specifically oriented crystalline structures
2Productivity
If the channel size is reduced to downscale the polycrystalline silicon transistor, then integration density increases, but the driving ability decreases due to reduced carrier mobility
Solution Approach 1:
By changing the crystal orientation parameter to <110> and controlling grain size parameters, the patent maintains high carrier mobility even when channel dimensions are reduced, enabling downsizing without sacrificing driving ability
3Reliability
If the grain size is increased to improve carrier mobility, then the channel mobility increases, but the chip surface area increases reducing integration density
Solution Approach 1:
The patent optimizes the grain size parameter to a specific range that provides sufficient carrier mobility while maintaining compact dimensions, and changes the crystal orientation to <110> to maximize mobility per unit area
Solution Approach 2:
The patent creates a composite structure with controlled grain distribution and specific crystal orientation that achieves high mobility in a compact area through the synergistic effect of grain boundary engineering and orientation control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases channel mobility and driving ability, reduces power consumption, and allows for both high driving capability and low power consumption while downsizing transistors, thereby enhancing memory integration and programming/reading speed without increasing chip surface area.
Implementation Method 1
an amorphous silicon layer is crystallized to form a polycrystalline silicon layer with a sufficient grain size
Implementation Method 2
reducing its thickness to maintain high channel mobility while increasing grain size
Data Source
AI summary
According to an embodiment, a semiconductor device includes an underlying layer and a plurality of transistors. The underlying layer includes a first region and a second region provided adjacently to the first region. The transistors are arranged in a plane parallel to an upper surface of the underlying layer. Each transistor includes a channel allowing a current to flow in a first direction intersecting the plane. The plurality of transistors includes a first transistor provided on the first region and a second transistor provided on the second region, a first channel of the first transistor having a first crystal orientation, and a second channel of the second transistor having a second crystal orientation different from the first crystal orientation.