Isolated Polysilicon Charge Storage Rings for Multi-Tier Memory
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Solution Overview
Problem
The fabrication of multi-tiered semiconductor devices is challenging due to difficulties in forming features in multiple tiers of semiconductor material, leading to high costs and inefficiencies, particularly in forming isolated charge storage structures that do not affect neighboring structures during programming or reading.
Innovation Solution
The process involves forming openings in a semiconductor construction with alternating tiers of polysilicon and dielectric, adding a p-type dopant to exposed polysilicon, removing the undoped polysilicon to create isolated doped polysilicon rings, and forming dielectrics and metal gates around these structures to isolate them electrically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-tiered semiconductor devices are fabricated using conventional methods, then charge storage structures can be formed, but fabrication complexity and cost increase significantly
Solution Approach 1:
The invention divides the semiconductor construction into alternating tiers of polysilicon and dielectric materials, creating discrete, isolated charge storage structures. Each polysilicon tier is separated by dielectric layers, allowing independent formation and electrical isolation of charge storage elements without requiring complex multi-step fabrication processes.
Solution Approach 2:
The patent extracts and removes undoped polysilicon portions after doping, leaving only the desired doped charge storage structures. This extraction step simplifies the final structure by eliminating unnecessary material, reducing fabrication complexity while maintaining the functional charge storage capability.
2Reliability
If features are formed in multiple tiers of semiconductor material, then charge storage structures can be created, but manufacturing cost increases
Solution Approach 1:
The invention combines multiple fabrication steps into a more integrated approach where polysilicon and dielectric tiers are formed in alternating sequences with simpler processing. The doping and selective removal steps are performed in a manner that consolidates operations, reducing the overall manufacturing cost while achieving reliable charge storage structure formation.
Solution Approach 2:
The patent applies different material properties locally by using alternating polysilicon and dielectric tiers. The polysilicon regions provide charge storage functionality while the dielectric regions provide electrical isolation and structural support. This local differentiation simplifies manufacturing by allowing standardized processes to be applied to each tier type rather than requiring complex integrated processing.
3Productivity
If polysilicon portions are not electrically isolated, then charge storage structures can be formed, but interference between adjacent structures occurs
Solution Approach 1:
The dielectric tiers serve as intermediary layers between adjacent polysilicon charge storage structures. These dielectric layers provide electrical isolation that prevents harmful interference between neighboring structures while allowing the polysilicon charge storage elements to function independently. The dielectric acts as a mediator that maintains the necessary electrical separation.
Solution Approach 2:
The invention segments the semiconductor construction into electrically isolated polysilicon regions separated by dielectric tiers. This segmentation ensures that charge storage structures in different tiers or adjacent to each other are electrically independent, preventing interference while maintaining high productivity in structure formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient formation of isolated charge storage structures that prevent electrical interference between neighboring structures, reducing the complexity and cost of semiconductor device fabrication while maintaining operational integrity.
Implementation Method 1
adding a p-type dopant to the exposed polysilicon
Data Source
AI summary
Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.