Polysilicon Contact CMP Using Oxide Slurry
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Solution Overview
Problem
Conventional semiconductor fabrication processes face challenges in achieving lower costs and higher complexity due to the limitations of device feature size reduction, with conventional polysilicon slurry showing high selectivity between polysilicon and borophosphosilicate glass, leading to undesirable dishing and erosion in semiconductor devices.
Innovation Solution
The use of an oxide slurry for chemical mechanical polishing of polysilicon contact structures in DRAM integrated circuits, allowing for the simultaneous polishing of polysilicon, borophosphosilicate glass, and silicon nitride, with the cap nitride layer serving as a polish stop, thereby reducing dishing and erosion and achieving higher throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional polysilicon slurry is used for chemical mechanical polishing, then high selectivity between polysilicon and borophosphosilicate glass is achieved, but dishing and erosion occur in the semiconductor devices
Solution Approach 1:
The invention changes the chemical composition parameters of the polishing slurry by using oxide slurry containing cerium oxide, aluminum oxide, or silicon oxide instead of conventional polysilicon slurry. This parameter change in slurry composition achieves high material selectivity for polishing polysilicon, BPSG, and silicon nitride simultaneously while preventing dishing and erosion defects in the semiconductor devices
Solution Approach 2:
The invention employs a disposable oxide-based polishing slurry that can be used universally for polishing multiple materials (polysilicon, BPSG, silicon nitride) without requiring material-specific slurry changes. This single-use oxide slurry approach eliminates the need for multiple specialized slurries and prevents cumulative dishing and erosion effects that occur with conventional polysilicon slurry
2Productivity
If device feature size is reduced to increase circuit density, then more devices can be packed onto a given chip area, but fabrication process limits are reached
Solution Approach 1:
The invention makes the oxide polishing slurry universal for polishing multiple different materials (polysilicon, BPSG, silicon nitride) in a single process step. This multi-functionality allows the fabrication process to maintain simplicity while achieving higher circuit density through reduced feature sizes, as the same slurry can handle various materials without requiring additional process steps or material-specific adjustments
3Productivity
If multiple materials are polished simultaneously, then throughput is improved, but achieving adequate critical dimension for gate silicon nitride becomes difficult
Solution Approach 1:
The oxide polishing slurry exhibits local quality in its polishing action by providing different removal rates for different materials based on their local chemical properties. The slurry is formulated to polish polysilicon, BPSG, and silicon nitride at controlled rates, with the cap nitride layer serving as a polish stop to protect the gate silicon nitride critical dimension while allowing throughput improvement from simultaneous multi-material polishing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method provides lower cost, improved material selectivity, reduced dishing and erosion, and higher device yields, while maintaining compatibility with conventional processes and equipment, achieving an adequate gate silicon nitride critical dimension and improved uniformity.
Implementation Method 1
The chemical mechanical polishing uses an oxide slurry rather than conventional polysilicon slurry
Data Source
AI summary
A method for fabricating an integrated circuit device. A plurality of MOS transistor devices are formed overlying a semiconductor substrate. Each of the MOS transistor devices includes a nitride cap and nitride sidewall spacers. An interlayer dielectric layer is formed overlying the plurality of MOS transistor devices. A portion of the interlayer dielectric material is removed to expose at least portions of three MOS transistor devices and expose at least three regions between respective MOS transistor devices. The method deposits polysilicon fill material overlying the exposed three regions and overlying the three MOS transistor devices. The method performs a chemical mechanical planarization process on the polysilicon material to reduce a thickness of the polysilicon material exposing a portion of the interlayer dielectric material until the cap nitride layer on each of the MOS transistors has been exposed using the cap nitride layer as a polish stop layer.