Polysilicon Diode Contact Trench Layout With Single-Mask Processing
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Solution Overview
Problem
Conventional semiconductor device manufacturing processes require additional steps and increased costs due to the need for multiple resist masks in forming contact holes and trenches, which can lead to decreased n-type impurity concentration and increased contact resistance, potentially affecting the diode's operation.
Innovation Solution
The semiconductor device design includes contact trenches and holes that penetrate through the polysilicon layer, with p+-type regions formed at the bottom and sidewalls of the trenches, allowing for a single resist mask to be used, reducing manufacturing steps and costs, while maintaining n-type conductivity and ensuring diode functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple resist masks are used to form contact holes and trenches, then the diode structure can be formed with proper insulation, but the manufacturing process becomes more complex and costly
Solution Approach 1:
The patent combines the formation of contact holes and contact trenches into a single etching process step. The contact holes penetrating the interlayer insulating film and the contact trenches penetrating the polysilicon layer are formed simultaneously, eliminating the need for separate resist masks and reducing manufacturing complexity while maintaining proper electrical insulation between the anode and cathode regions.
Solution Approach 2:
The single resist mask pattern is designed to serve multiple functions: it defines both the contact hole openings through the interlayer insulating film and the contact trench openings through the polysilicon layer. This multi-functional pattern reduces the number of photolithography steps required while ensuring proper alignment and insulation for diode operation.
2Reliability
If additional manufacturing steps are introduced to ensure proper insulation, then diode functionality is maintained, but production time and costs increase
Solution Approach 1:
The interlayer insulating film is formed beforehand to cover the polysilicon layer before the contact holes and trenches are etched. This preliminary insulation layer ensures that when the contact holes and trenches are formed in a single step, electrical insulation is already in place, preventing short circuits between the anode and cathode regions while maintaining high manufacturing efficiency.
Solution Approach 2:
The insulation structure is segmented into distinct layers: the interlayer insulating film covering the polysilicon layer and the contact holes/trenches penetrating through these layers. This segmentation allows the insulation function to be performed by the interlayer insulating film while the contact structures provide electrical access, achieving both reliability and productivity.
3Manufacturing precision
If conventional multi-step processes are used, then precise control of impurity concentration is possible, but contact resistance increases due to process variations
Solution Approach 1:
The etching process forms both the contact holes through the interlayer insulating film and the contact trenches through the polysilicon layer in a continuous, single operation. This continuity eliminates interruptions and re-alignments between steps, reducing process variations that could affect impurity concentration and contact resistance, while maintaining precise control through the single resist mask pattern.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs by eliminating the need for multiple resist masks and ensures accurate temperature measurement and reduced contact resistance, enabling efficient and cost-effective production of semiconductor devices with integrated temperature sensors.
Implementation Method 1
Current/voltage characteristics of the pn junction diode vary depending on temperature and thus, the device temperature of the power semiconductor device may be detected from temperature characteristics of the pn junction diode
Implementation Method 2
a first first-conductivity-type high-concentration region selectively provided in the polysilicon layer and being in contact with the first-conductivity-type region, so as to be in direct contact with a bottom, sidewalls or both the bottom and the sidewalls of the first contact trench
Data Source
AI summary
A diode formed by a polysilicon layer is disposed between a field oxide film and an interlayer insulating film, in a semiconductor substrate, at a front surface of the semiconductor substrate. One resist mask is used to form contact holes of the interlayer insulating film and contact trenches and a p+-type region of the polysilicon layer. The contact trenches are continuously formed from bottoms of the contact holes, respectively, in a depth direction. A low-resistance contact between the p+-type region and an anode electrode is formed at least at a bottom of the contact trench. During the formation of the p+-type region, while a p-type impurity is ion-implanted in an inner wall of the contact trench 3b, an n-type cathode region maintains an n-type conductivity thereof and a contact with a cathode electrode is formed at sidewalls of the contact trench.