Polysilicon Diode Program Selector for Compact Resistive Memory
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Solution Overview
Problem
Conventional programmable resistive memory devices, such as those using NMOS or bipolar transistors as program selectors, face challenges in reducing cell size and cost, particularly in embedded applications, due to the need for large program selectors and complex fabrication processes.
Innovation Solution
The use of polysilicon diodes as program selectors in standard CMOS logic processes, where P+ and N+ implants are used to create sources or drains of MOS devices, allowing for smaller cell sizes and reduced costs without additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NMOS or bipolar transistors are used as program selectors, then reliable current control is achieved, but cell size increases and fabrication complexity increases
Solution Approach 1:
The patent extracts the program selector function from complex transistor structures and implements it using simple diodes formed by P+ and N+ implants in standard CMOS processes. This extraction maintains the essential current control function while eliminating the need for complex gate structures, thereby reducing fabrication complexity and cell size.
Solution Approach 2:
The patent employs simple diodes made from standard CMOS implant processes as program selectors, replacing expensive and complex transistor-based selectors. These diode structures, formed through routine P+ and N+ implantation, provide sufficient current control for programming while being much simpler and less costly to fabricate.
2Reliability
If NMOS or bipolar transistors are used as program selectors, then reliable current control is achieved, but cell size increases
Solution Approach 1:
The patent removes the complex transistor gate structures and uses only the essential diode structures formed by P+ and N+ implants. This extraction of the core function into simpler elements dramatically reduces the area required for program selectors, thereby shrinking the overall memory cell size while maintaining current control capability.
Solution Approach 2:
By replacing large transistor structures with compact diodes formed through standard implant processes, the patent achieves significant area reduction. The simple diode structures require minimal space compared to full transistor gates and contacts, enabling smaller memory cell footprint.
3Manufacturing precision
If special processing or masks are used for diode formation, then precise doping control is achieved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent makes the P+ and N+ implants serve dual purposes: forming both the diode structures and the source/drain regions of MOS devices. This multi-functionality eliminates the need for separate diode formation processes and masks, achieving precise doping control through standard CMOS processes while maintaining ease of manufacture.
Solution Approach 2:
The patent merges the diode formation process with the standard MOS device fabrication process. By using the same P+ and N+ implant steps for both diodes and MOS source/drain regions, the patent combines what would otherwise be separate processes into a single integrated flow, eliminating additional masks and steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of compact programmable resistive memory cells with reduced costs, as the same polysilicon can be used for CMOS gates, achieving smaller cell sizes and lower fabrication costs by eliminating the need for special processing or masks.
Implementation Method 1
at least one diode as program selectors; wherein the first and second terminals of the diode with a first and second types of dopants
Data Source
AI summary
A method and system for multiple-bit programmable resistive cells having a multiple-bit programmable resistive element and using diode as program selector are disclosed. The first and second terminals of the diode having a first and second types of dopants can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure. If a multiple-bit programmable resistive cell has 2n (n>1) distinct resistance levels to store n-bit data, at least 2n−1 reference resistance levels can be designated to differential resistances between two adjacent states. Programming multiple-bit programmable resistive elements can start by applying a program pulse with initial program voltage (or current) and duration. A read verification cycle can follow to determine if the desirable resistance level is reached. If the desired resistance level has not been reached, additional program pulses can be applied.