Polysilicon Doping Control for 3D NAND Etching
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Solution Overview
Problem
Cross word line cell variability in 3D NAND memory structures leads to inconsistent program and erase voltages, affecting memory cell reliability due to variations in control gate recess (CGR) critical dimension and inter-poly dielectric layer thickness.
Innovation Solution
Adjusting the dopant concentration in word line layers during the fabrication process to optimize CGR shaping and inter-poly dielectric layer thickness, using in-situ deposition to ensure consistent CGR formation and improved etch profiles, thereby decoupling CGR critical dimension from incoming etch conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If standard doping concentration is used in word line layers, then fabrication process is simple, but CGR critical dimension uniformity deteriorates
Solution Approach 1:
The patent applies local quality by implementing different doping concentrations in different word line layers. Specifically, lower word line layers (e.g., WL0-WL7) receive a first doping concentration while upper word line layers (e.g., WL8-WL15) receive a second doping concentration. This localized variation in doping quality optimizes CGR etching profiles at different depths, improving CGR critical dimension uniformity throughout the 3D NAND structure.
Solution Approach 2:
The patent changes the doping concentration parameter across different word line layers to control etch rates. By adjusting the doping concentration from 1×10^20 atoms/cm³ to 1×10^21 atoms/cm³ in different layers, the etch profile is optimized to achieve consistent CGR dimensions despite variations in etch conditions at different depths in the stacked structure.
2Reliability
If uniform doping is applied across all word line layers, then process complexity is reduced, but program and erase voltage stability deteriorates
Solution Approach 1:
Different doping concentrations are applied to different word line layers to stabilize program and erase voltages. The lower word line layers use one doping concentration while upper layers use another, creating localized electrical properties that compensate for voltage variations across the vertical stack, thereby improving overall reliability.
Solution Approach 2:
The doping concentration parameter is varied across word line layers to control electrical characteristics. This parameter change ensures that program and erase voltages remain stable across all memory cells in the 3D NAND structure, preventing variability that would otherwise occur in deep stacked architectures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity of CGR formation, stabilizes program and erase voltages, and improves memory cell reliability by reducing variability in 3D NAND memory structures.
Implementation Method 1
adjusting the doping of the polysilicon word line layers as they are being deposited
Data Source
AI summary
A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. A first portion of the plurality of doped semiconductor material layers may be doped with a first dopant having a first dopant parameter. A second portion of the plurality of doped semiconductor material layers may be doped with a second dopant having a second dopant parameter. In embodiments, the first portion of the plurality of doped semiconductor layers may include a dopant at a concentration less than a defined threshold. In embodiments, the second portion of the plurality of doped semiconductor layers may include a dopant at a concentration less than the defined threshold. The differing dopant concentrations have been found to beneficially and advantageously affect the etch rate in the respective semiconductor layers when forming control gate recesses in the semiconductor layers.