Polysilicon Layer Doping for RF Substrate Resistivity
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Solution Overview
Problem
High resistivity Silicon On Insulator (SOI) substrates used in radiofrequency applications suffer from parasitic surface conduction due to fixed oxide charges, which reduce effective resistivity and limit performance, especially for next-generation RF components, and the introduction of a polycrystalline silicon layer to trap these charges leads to recrystallization issues that decrease trapping efficiency with increased thickness.
Innovation Solution
Incorporating carbon and/or nitrogen atoms at grain boundaries of the polycrystalline silicon layer to slow down recrystallization kinetics, allowing for a thinner polysilicon layer that maintains trapping efficiency and reduces surface roughness, with a thickness ranging from 200 to 1000 nm, and potentially including a nitrogen-free portion to minimize recrystallization and enhance uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polycrystalline silicon layer is introduced to trap electrical charges and improve effective resistivity, then the substrate's RF performance is improved, but the layer thickness must be increased to maintain trapping efficiency, which increases surface roughness and polishing requirements
Solution Approach 1:
The patent changes the chemical composition parameters of the polysilicon layer by incorporating carbon and nitrogen atoms at grain boundaries. This modifies the recrystallization kinetics, allowing a thinner layer (200-1000 nm) to maintain trapping efficiency without excessive surface roughness. The carbon/nitrogen concentration acts as a controllable parameter to optimize both thickness and trapping performance.
Solution Approach 2:
The patent applies local quality by concentrating carbon and nitrogen atoms specifically at the grain boundaries of the polysilicon layer rather than uniformly throughout. This localized doping approach maximizes the slowing of recrystallization kinetics at the critical trapping interfaces while minimizing overall layer thickness and surface roughness.
2Reliability
If the polysilicon layer thickness is increased to maintain trapping efficiency, then charge trapping is improved, but surface roughness increases and polishing requirements increase
Solution Approach 1:
By modifying the chemical composition (adding carbon and nitrogen) rather than increasing thickness, the patent achieves the same trapping efficiency with a thinner layer. This parameter change directly reduces surface roughness and polishing requirements while maintaining the necessary charge trapping capability.
3Strength
If high temperature heat treatment is applied to reinforce bonding strength, then bonding is improved, but recrystallization of the polysilicon layer occurs which reduces trapping efficiency
Solution Approach 1:
The patent applies preliminary anti-action by pre-doping the polysilicon layer with carbon and nitrogen atoms before the high-temperature bonding process. This preliminary modification creates resistance to recrystallization, counteracting the harmful effect of subsequent high-temperature heat treatment and preserving trapping efficiency throughout the manufacturing process.
Solution Approach 2:
The carbon and nitrogen concentration in the polysilicon layer is adjusted to optimize the balance between bonding strength and recrystallization resistance. This parameter modification allows the layer to withstand high-temperature bonding while maintaining its polycrystalline structure and trapping capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enables efficient trapping of electrical charges with a reduced polysilicon layer thickness, minimizing surface roughness and polishing requirements, while maintaining or improving RF performance by preserving the number of grain boundaries, thus enhancing the substrate's resistivity and reliability.
Implementation Method 1
Incorporating carbon and/or nitrogen atoms at grain boundaries of the polycrystalline silicon layer to slow down recrystallization kinetics
Implementation Method 2
a polycrystalline silicon layer is introduced between the dielectric layer and the high resistivity base substrate, to provide a trap-rich layer underneath the dielectric layer to freeze the PSC
Data Source
Figure 1~4A
Figure 4B~4D
AI summary
The invention relates to a structure (100) for radiofrequency applications comprising: - a monocrystalline substrate (1), - a polycrystalline silicon layer (2) directly on the monocrystalline substrate (1), - an active layer (3) on the polycrystalline silicon layer (2), intended to receive radiofrequency components, characterized in that at least a first portion (2a) of the polycrystalline silicon layer (2) extending from the interface (I) of the polycrystalline silicon layer (2) with the monocrystalline layer includes carbon and/or nitrogen atoms located at the grain boundaries of the polycrystalline silicon. The invention further relates to a process for manufacturing such a structure.