Polysilicon Emitter Biristor for Low-Voltage DRAM Reliability
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Solution Overview
Problem
Conventional DRAM devices face challenges in miniaturization of capacitors while maintaining capacitance, leading to reliability and durability issues due to high driving voltages required for memory state operations in capacitorless DRAMs.
Innovation Solution
A two-terminal biristor is designed with a polysilicon layer inserted between the emitter semiconductor region and the metallic layer to increase current gain, decrease latch-up and latch-down voltages, and expand the latch voltage window, manufactured through methods such as ion implantation or epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If capacitorless DRAM is used for miniaturization, then cell size is reduced and integration is improved, but high driving voltage is required causing gate insulating layer deterioration
Solution Approach 1:
A polysilicon layer is introduced as an intermediary between the emitter semiconductor region and the metallic layer. This intermediate layer modifies the electrical characteristics at the interface, enabling lower operating voltages that prevent gate insulating layer deterioration while maintaining the capacitorless DRAM structure for miniaturization.
Solution Approach 2:
The polysilicon layer changes the electrical parameters (current gain, latch-up voltage, latch-down voltage) of the biristor structure. By adjusting these parameters through the polysilicon layer, the device operates at lower voltages, solving the reliability issue while preserving the miniaturized cell structure.
2Power
If polysilicon layer is inserted to increase current gain, then latch-up voltage and latch-down voltage decrease and latch voltage window increases, but device structure becomes more complex
Solution Approach 1:
The emitter region is segmented by introducing a distinct polysilicon layer between the emitter semiconductor region and metallic layer. This segmentation allows independent optimization of electrical characteristics while maintaining a relatively simple overall device structure suitable for manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances current gain, reduces latch-up and latch-down voltages, and increases the latch voltage window, enabling low-power driving and improving the reliability and durability of memory devices like DRAMs.
Implementation Method 1
a polysilicon layer is inserted between an emitter semiconductor region and a metallic layer to increase a current gain
Implementation Method 2
forming a first semiconductor layer of a first type on a substrate, forming a second semiconductor layer of a second type on the first semiconductor layer, and forming a third semiconductor layer of the first type on the second semiconductor layer
Data Source
AI summary
A two-terminal biristor in which a polysilicon emitter layer is inserted and a method of manufacturing the same are provided. The method of manufacturing the two-terminal biristor according to an embodiment of the present disclosure includes forming a first semiconductor layer of a first type on a substrate, forming a second semiconductor layer of a second type on the first semiconductor layer, forming a third semiconductor layer of the first type on the second semiconductor layer, and forming a polysilicon layer of the first type on the third semiconductor layer.