Polysilicon Etch Profile Control in FinFET Gate Structures

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The semiconductor industry faces challenges in achieving precise etch profile control for polysilicon structures within high aspect ratio spaces between fin structures of IO and non-IO finFETs, leading to potential damage and residual polysilicon issues that affect device performance and reliability.

Innovation Solution

The method involves forming protective oxide layers with varying thicknesses on top surfaces and sidewalls of fin structures, allowing for extended etching times without damaging the fins and reducing polysilicon residues, thereby improving etch profiles and subsequent gate structure formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If etching is performed to remove polysilicon structures, then polysilicon residues are reduced, but fin structures may be damaged due to extended etching times

Engineering Contradiction:

Improveetch profile controlVSAvoidfin structure integrity

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

A protective oxide layer is deposited on the fin structures to serve as an intermediary barrier during polysilicon etching. This oxide layer protects the fin structures from direct exposure to etchants, enabling extended etching times to remove polysilicon residues without damaging the underlying fin structures. The protective oxide layer is selectively removed afterward to expose the fin structures.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The protective oxide layer is formed in advance before the polysilicon etching process. This preliminary protective action ensures that when etching is performed to remove polysilicon residues, the fin structures are already shielded and can withstand the extended etching duration without damage.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If protective oxide layers are formed on fin structures, then fin structures are protected during etching, but device complexity increases

Engineering Contradiction:

Improvefin structure protectionVSAvoidprocess steps

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The protective oxide layer serves multiple functions: it protects fin structures during polysilicon etching, enables extended etching times for complete residue removal, and can be selectively removed to expose fin structures. By combining these functions into a single layer, the patent reduces overall process complexity despite adding the protective layer formation step.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Manufacturing precision

If extended etching is performed to remove polysilicon residues, then etch profiles are improved, but fin structures may be damaged

Engineering Contradiction:

Improvepolysilicon residue removalVSAvoidfin structure damage

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The protective oxide layer is deposited beforehand to cushion and absorb the harmful effects of extended etching on fin structures. This pre-established protection allows the etching process to proceed for sufficient duration to remove all polysilicon residues without the fin structures being exposed to damaging etchant concentrations.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the etch profiles of polysilicon structures, reduces polysilicon residues, and improves the performance and reliability of IO and non-IO finFETs by minimizing current leakage between source/drain and gate structures.

Implementation Method 1

forming protective oxide layers with varying thicknesses on top surfaces and sidewalls of fin structures, allowing for extended etching times without damaging the fins

Methodology Applied

Scientific EffectPhysical barrier protection:

Implementation Method 2

Etch Profile Control of Polysilicon Structures of Semiconductor Devices

Methodology Applied

Scientific EffectChemical etching:

Data Source

PatentUS20250023255A1Etch Profile Control Of Polysilicon Structures Of Semiconductor Devices

Publication Date: 2025.01.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions. The method also includes forming first and second source/drain regions on first and second recessed portions of the first and second fin structures, respectively and replacing the first and second polysilicon structures with first and second gate structures, respectively.