Polysilicon Etch Temperature Control for SSD Recess Precision
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in fabricating FinFET devices due to increased complexity and reduced feature sizes, leading to manufacturing defects and variability in device performance, particularly in controlling the strained source drain (SSD) profile and epitaxial volume, which affects mobility and topography.
Innovation Solution
The method involves controlling etch chamber conditions to improve the SSD profile through temperature management, using a heating apparatus to maintain a polymerizing temperature that promotes polymeric deposits on horizontal surfaces, reducing over-etch and undercutting, and thereby enhancing the control of SSD recess dimensions and epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to remove polysilicon, then material removal is achieved, but dimensional control of the etched features deteriorates due to over-etch and undercutting
Solution Approach 1:
The patent changes the temperature parameter during the etching process by heating the reactor chamber to a polymerization temperature. This parameter change promotes polymeric deposit formation on horizontal surfaces, which acts as a protective layer that prevents over-etch and undercutting, thereby improving dimensional control of the etched features
Solution Approach 2:
The patent converts the typically harmful effect of polymeric deposits (which can cause spacing issues) into a beneficial protective layer. By controlling the deposition through temperature management, the polymeric material that would normally be considered a defect instead becomes a protective coating that prevents harmful over-etch and undercutting at the etched features
2Productivity
If feature sizes are reduced to increase device density, then higher device density is achieved, but manufacturing defects increase due to process variability
Solution Approach 1:
The patent applies temperature parameter changes during etching to improve dimensional control and reduce process variability. By heating the reactor chamber to promote controlled polymeric deposition, the process achieves better consistency in etched feature dimensions, which directly reduces manufacturing defects even as feature sizes are reduced for higher device density
3Ease of manufacture
If etching is performed without temperature control, then process simplicity is maintained, but polymeric deposit formation on horizontal surfaces is uncontrolled leading to spacing issues
Solution Approach 1:
The patent introduces temperature control as a process parameter, heating the reactor chamber to a polymerization temperature. This controlled temperature parameter enables precise control over polymeric deposit formation on horizontal surfaces, ensuring that deposits form at controlled rates and locations, thereby improving spacing control while maintaining reasonable process simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing defects, improves device mobility, and achieves more controlled epitaxial volume and topography, leading to better manufacturing yield and performance of FinFET devices.
Implementation Method 1
heating the reactor chamber to establish a polymerization temperature Tp within the reactor chamber during a second portion of the etch period
Implementation Method 2
exposing the wafer to an activated etchant within the reactor chamber for a first portion of an etch period to remove polysilicon
Data Source
AI summary
Provided are methods of manufacturing integrated circuit that include a polysilicon etch process in which the wafer having an etch poly pattern is loaded into a reactor chamber and exposed to an activated etchant and, during the etch process, adjusting the temperature conditions within the reactor chamber to increase polymeric deposition on an upper surface of the wafer.