Polysilicon Feature Dimension Control via Two-Step Etching
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Solution Overview
Problem
Traditional semiconductor manufacturing processes face inefficiencies due to inconsistent and non-repeatable measurement of critical dimensions, particularly in polysilicon gate lines, leading to waste of sacrificial wafers and suboptimal compensation for lithography drifts.
Innovation Solution
Implementing a two-step etching process that separates material line pattern etching into reactive ion etching followed by chemical downstream etching, allowing for feed-forward measurement and adjustment of etch control parameters to compensate for dimensional variations without the need for a sacrificial send-ahead wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a send-ahead wafer is used to test-run manufacturing processes for adjustment, then manufacturing process control is improved, but manufacturing efficiency deteriorates due to wafer waste
Solution Approach 1:
The system uses measurements from actual production wafers to automatically adjust process parameters for subsequent wafers, eliminating the need for separate sacrificial test wafers. Each wafer contributes to process optimization while remaining marketable, achieving self-service process control.
Solution Approach 2:
The system implements a feedback loop where measurements of actual feature dimensions on production wafers are used to calculate adjustments to process parameters. This closed-loop control enables continuous process optimization without requiring sacrificial wafers, resolving the contradiction between precision control and manufacturing efficiency.
2Manufacturing precision
If traditional single-step etching is used, then process simplicity is maintained, but dimensional control accuracy deteriorates
Solution Approach 1:
The etching process is divided into two distinct steps: reactive ion etching (RIE) followed by chemical downstream etching (CDE). This segmentation allows each step to contribute differently to the final dimension, with RIE providing anisotropic etching and CDE providing isotropic etching for precise critical dimension control.
Solution Approach 2:
The system dynamically adjusts etching parameters including power, pressure, gas flow rates, and temperature based on measured feature dimensions. These parameter changes enable precise control of polysilicon feature dimensions by compensating for variations in each etching step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate and repeatable control of polysilicon feature dimensions, reducing waste and improving the efficiency of semiconductor manufacturing by allowing each wafer in a run to be marketable, eliminating the need for a sacrificial wafer and enhancing dimensional metrology accuracy.
Implementation Method 1
a first etch system configured to etch a layer to define a pattern in the layer
Implementation Method 2
a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter
Data Source
AI summary
A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.