Polysilicon Semiconductor Layer Formation on Flexible Substrates
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Solution Overview
Problem
The formation of a polysilicon semiconductor layer on a flexible display device substrate is prone to damage due to temperature fluctuations during the activation process, affecting the reliability and manufacturing efficiency of the transistor.
Innovation Solution
A display device structure featuring a flexible substrate with a polysilicon semiconductor layer, including a passivation layer, alignment members, insulation layers, and electrodes, where the semiconductor layer is formed by sequentially doping and crystallizing an amorphous silicon material layer, reducing the need for additional activation processes and minimizing substrate damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an amorphous silicon material layer is formed and crystallized to create a polysilicon semiconductor layer, then the semiconductor layer can be formed on a flexible substrate, but the substrate is prone to damage due to temperature fluctuations during the activation process
Solution Approach 1:
The patent applies preliminary action by forming the semiconductor layer with appropriate doping concentration and crystalline structure before the activation process. The semiconductor layer is prepared in advance with controlled impurity content, so that during subsequent activation at high temperatures, the substrate is less susceptible to damage because the layer is already optimized for thermal processing.
Solution Approach 2:
The patent changes parameters by controlling the doping concentration of the semiconductor layer within specific ranges (1×10^19 to 1×10^21 atoms/cm³) and adjusting crystallization conditions. By optimizing these parameters before activation, the semiconductor layer becomes more resistant to temperature-induced substrate damage while maintaining reliable transistor operation.
2Reliability
If additional activation processes are performed to activate the polysilicon semiconductor layer, then the transistor reliability is improved, but the manufacturing process becomes more complex and time-consuming
Solution Approach 1:
The patent merges the crystallization process with the activation process into a single integrated step. By controlling the doping concentration and crystalline structure during the initial formation, the semiconductor layer can be activated during the same thermal processing without requiring separate activation steps, thereby simplifying the manufacturing process while maintaining transistor reliability.
Solution Approach 2:
The patent performs preliminary doping and crystallization to prepare the semiconductor layer in advance with optimal properties. This preliminary preparation ensures that the layer is ready for activation during standard thermal processing, eliminating the need for additional dedicated activation processes and reducing manufacturing complexity.
3Reliability
If the semiconductor layer is heavily doped to reduce leakage current, then transistor reliability is improved, but parasitic capacitance increases
Solution Approach 1:
The patent optimizes the doping concentration parameter within a specific range (1×10^19 to 1×10^21 atoms/cm³) rather than using extreme heavy doping. This controlled parameter adjustment reduces leakage current to acceptable levels while avoiding the excessive parasitic capacitance that would result from much higher doping concentrations, achieving a balanced optimization.
Solution Approach 2:
The patent applies different doping concentrations to different regions of the semiconductor layer. By creating local variations in doping levels, the patent can reduce leakage current in critical regions while maintaining lower doping in other areas to minimize parasitic capacitance, thus achieving both reliability improvement and harmful factor reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of the transistor by reducing leakage current and parasitic capacitance, while simplifying the manufacturing process and maintaining the flexibility of the substrate.
Implementation Method 1
an amorphous silicon material layer is formed and then crystallized
Implementation Method 2
injecting a conductive impurity to the amorphous silicon material layer through a first doping process
Data Source
AI summary
A display device includes: a flexible substrate; a semiconductor layer on the flexible substrate; a passivation layer on the semiconductor layer; an alignment member layer on the passivation, the alignment member layer including a first alignment member and a second alignment member in a same layer; a first insulation layer on the alignment member layer and the passivation layer; a gate electrode on the first insulation layer; a second insulation layer on the first insulation layer and the gate electrode; and a source electrode and a drain electrode on the second insulation layer and spaced apart from each other, wherein the first alignment member and the second alignment member are spaced apart from each other with the gate electrode therebetween.