Polysilicon Gate Over-Polishing Prevention in Metal-Gate CMP
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional chemical mechanical polishing (CMP) processes for semiconductor devices result in over-polishing of polysilicon gates due to higher removal rates for polysilicon compared to metal materials, leading to performance degradation and yield reduction.
Innovation Solution
A method involving multiple CMP processes with specific slurry types, such as A7100 from Cabot Microelectronics Corporation, and the use of hard mask layers to control the height and exposure of gate electrodes, ensuring that the polysilicon gates are not excessively polished, and forming metal gate layers with work function metals like aluminum.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional CMP process with polysilicon-removal slurry is used to polish aluminum gates, then the aluminum gate polishing is effective, but the polysilicon gate and dummy gate are over-polished leading to performance degradation
Solution Approach 1:
The patent applies different slurry types to different regions: a first slurry with lower polysilicon removal rate is used when polishing both aluminum and polysilicon gates together, while a second slurry with higher polysilicon removal rate is used only for aluminum gate polishing after the polysilicon gate has been protected or removed. This local differentiation of polishing conditions resolves the contradiction by ensuring each gate type receives appropriate polishing treatment.
Solution Approach 2:
The patent segments the CMP process into multiple stages: first polishing both aluminum and polysilicon gates with a protective slurry, then performing a second polishing step for aluminum gates with a more aggressive slurry. This segmentation allows the process to achieve both aluminum gate precision and polysilicon gate protection.
2Productivity
If a CMP slurry with high polysilicon removal rate is used, then the polishing efficiency is improved, but the polysilicon gate and dummy gate are excessively removed
Solution Approach 1:
The patent performs a preliminary polishing step using a slurry with lower polysilicon removal rate before applying the high-efficiency slurry. This preliminary action removes a small controlled amount of polysilicon and creates a protective layer or modifies the surface to prevent excessive removal during the subsequent high-efficiency polishing step.
Solution Approach 2:
The patent intentionally allows slight over-polishing in the first step with the lower-removal slurry, then compensates in the second step by using process controls and shorter polishing times with the high-removal slurry, achieving overall precise dimension control while maintaining high productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents over-polishing of polysilicon gates, thereby improving the performance and yield of semiconductor devices by maintaining the desired dimensions and structures during the CMP processes.
Implementation Method 1
performing a first chemical mechanical polishing (CMP) process on the interlayer dielectric layer to expose a surface of the first gate and a surface of the second gate
Implementation Method 2
removing the first gate by etching using the hard mask layer as a mask to form a trench
Data Source
AI summary
A method for manufacturing a semiconductor device includes providing a substrate containing a front-end device that includes a first gate in a first-type transistor region and a second gate in a second-type transistor region, forming an interlayer dielectric layer on the semiconductor substrate, and planarizing the interlayer dielectric layer to expose the surface of the first and second gates. The method also includes forming a hard mask layer on the second gate, removing the first gate using the hard mask layer as a mask to form a trench, forming sequentially a work function metal layer and a metal gate layer in the trench, and removing a portion of the first work function metal layer and a portion of the metal gate layer that are higher than the interlayer dielectric layer to form a metal gate.