Polysilicon Gate Electrode Impurity Interdiffusion Control
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Solution Overview
Problem
The existing PN dual gate process for manufacturing semiconductor devices results in variation in threshold voltage (Vt) due to interdiffusion of impurities during thermal treatment, leading to inconsistent transistor properties.
Innovation Solution
A method involving the formation of a gate electrode with a stacked structure of a polysilicon film, a metal silicide film, a metal nitride film, and a metal film, where impurities are introduced and diffused without interdiffusion by performing thermal treatment after separating the metal silicide film portions for P-type and N-type MOSFETs, ensuring uniform impurity distribution and preventing shifts in Vt.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thermal treatment is performed to diffuse impurities in the polysilicon film after doping both N-type and P-type impurities, then uniform impurity distribution is achieved, but impurity interdiffusion occurs between N-type and P-type regions causing threshold voltage variation
Solution Approach 1:
The patent segments the metal silicide film into separate P-type and N-type regions before thermal treatment. By forming separate metal silicide regions that correspond to P-type and N-type impurity doped polysilicon regions, the patent prevents interdiffusion of impurities between opposite-type regions during thermal processing, while still achieving uniform impurity distribution within each type region.
Solution Approach 2:
The patent performs preliminary patterning of the metal silicide film into separate P-type and N-type regions before introducing and diffusing impurities. This preliminary segmentation ensures that when thermal treatment is applied to diffuse impurities for uniform distribution, the impurities remain confined to their respective type regions and cannot interdiffuse into opposite-type regions.
2Reliability
If a three-layer polymetal gate structure with barrier layer is formed to reduce interface resistance, then adhesivity between polysilicon and refractory metal is improved, but process complexity increases
Solution Approach 1:
The patent applies local quality by forming metal silicide regions with different conductivity types (P-type and N-type) in different local areas of the gate structure. Each region is doped with appropriate impurities to achieve optimal electrical properties for its specific function, while maintaining the overall simplicity of the gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces variation in transistor properties by eliminating impurity interdiffusion, resulting in stable and consistent transistor performance.
Implementation Method 1
performing thermal treatment after introducing the impurities into the polysilicon film
Implementation Method 2
diffuse the impurities introduced in the polysilicon film
Implementation Method 3
Directly forming the tungsten nitride film on the impurity-doped polysilicon film using PVD (Physical Vapor Deposition), such as sputtering
Implementation Method 4
Directly forming the tungsten nitride film on the impurity-doped polysilicon film using PVD (Physical Vapor Deposition), such as sputtering
Data Source
AI summary
A method for manufacturing a semiconductor device having a P-type MOSFET and an N-type MOSFET, the method comprising the steps of: forming a gate insulating film, a non-doped polysilicon film, a metal silicide film, a metal nitride film and a metal film on a semiconductor substrate; processing at least the metal film, the metal nitride film and the metal silicide film to pattern them into the shape of a gate such that the portion of the meal silicide film that forms part of a gate electrode of a P-type MOSFET and the portion of the meal silicide film that forms part of a gate electrode of an N-type MOSFET are separated from each other; introducing P-type and N-type impurities into the respective regions of the non-doped polysilicon film where the P-type and N-type MOSFETs are formed; performing thermal treatment to diffuse the impurities; and patterning the polysilicon film with the impurities introduced into the shape of the gate.