Polysilicon Gate Electrode for Wide-Gap Semiconductor Reliability

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Solution Overview

Problem

Wide-gap semiconductor devices with metallic Schottky electrodes below the gate pad face manufacturing complexity and high costs, leading to abnormal potential increases in the well region due to high sheet resistance.

Innovation Solution

A wide-gap semiconductor device with a polysilicon layer between well regions and a drift layer, an interlayer insulating film, and a gate pad, where the polysilicon layer is in Schottky contact with the drift layer, reducing sheet resistance and manufacturing complexity by using polysilicon instead of metallic materials.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a Schottky electrode formed of a metallic material is used below the gate pad, then the sheet resistance is reduced, but the manufacturing complexity and cost increase considerably

Engineering Contradiction:
Improvesheet resistanceVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces expensive metallic Schottky electrodes with a polysilicon layer that can be formed using standard semiconductor manufacturing processes. The polysilicon layer, though having different electrical characteristics, provides sufficient performance for the application while dramatically reducing manufacturing complexity and cost.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the material parameter from metallic material to polysilicon, and adjusts the doping concentration of the polysilicon layer to optimize its electrical properties. By controlling the doping concentration, the polysilicon layer achieves appropriate sheet resistance values without requiring complex metallic electrode structures.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If a well region of a second conductivity type is provided below the gate pad, then the device structure is formed, but the potential in the well region abnormally increases due to displacement current during switching operation

Engineering Contradiction:
Improvewell region structureVSAvoidpotential stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces a polysilicon layer as an intermediary between the well region and the gate pad. This polysilicon layer acts as a potential equalization path, allowing displacement current to flow through it during switching operations, thereby preventing abnormal potential increases in the well region while maintaining the necessary device structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The polysilicon layer is designed to maintain equipotential conditions in the region below the gate pad during switching operations. By providing a conductive path with appropriate resistance, the polysilicon layer ensures that the well region remains at a stable potential, preventing the abnormal potential increases that would otherwise occur.

Inventive Principle:
Principle #12Equipotentiality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The polysilicon layer effectively prevents abnormal potential increases below the gate pad, reduces manufacturing costs, and simplifies the manufacturing process while maintaining low contact resistance, thereby improving the performance and efficiency of the semiconductor device.

Implementation Method 1

the polysilicon layer and the drift layer may be in Schottky contact

Methodology Applied
Scientific EffectSchottky contact:

Data Source

PatentUS11264494B2Wide-gap semiconductor device
Publication Date: 2022.03.01 SHINDENGEN ELECTRIC MANUFACTURING CO LTD
  • US11264494B2 patent drawing
  • US11264494B2 patent drawing
  • US11264494B2 patent drawing

AI summary

A wide gap semiconductor device has: a drift layer 12 using wide gap semiconductor material being a first conductivity type; a plurality of well regions 20 being a second conductivity type and formed in the drift layer 12; a polysilicon layer 150 provided on the well regions 20 and on the drift layer 12 between the well regions 20; an interlayer insulating film 65 provided on the polysilicon layer 150; a gate pad 120 provided on the interlayer insulating film 65; and a source pad 110 electrically connected to the polysilicon layer 150.