Polysilicon Gate Footing Profile for Low Leakage MOS Devices
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Solution Overview
Problem
Conventional polysilicon gate processing techniques face limitations in reducing device line width, leading to challenges in achieving improved device performance and increased circuit density due to constraints in polysilicon gate geometry.
Innovation Solution
A method and structure for fabricating a polysilicon gate with a specific footing profile, utilizing a simulation model to determine device performance and provide a process control window, allowing for the fabrication of MOS devices with enhanced characteristics such as reduced threshold leakage current and improved saturation current, while being compatible with conventional technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If polysilicon gate processing is used to reduce device line width, then device geometry is improved, but manufacturing precision deteriorates due to process limitations
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before the polysilicon gate deposition. This mandrel serves as a pre-established template that guides the subsequent polysilicon deposition process, ensuring that the polysilicon gate achieves the desired geometry even at reduced line widths. The mandrel is removed after serving its purpose, leaving a precisely formed polysilicon gate structure.
Solution Approach 2:
The patent introduces an intermediary element - the mandrel - that mediates between the deposition process and the final polysilicon gate structure. This intermediary structure enables precise control of polysilicon gate geometry during deposition, allowing manufacturing precision to be maintained even as device line width is reduced. The mandrel acts as a temporary scaffold that is removed after transferring its geometric information to the polysilicon gate.
2Productivity
If device line width is reduced to increase circuit density, then productivity is improved, but device performance deteriorates due to process limitations
Solution Approach 1:
By pre-forming the mandrel structure with the exact desired geometry before polysilicon deposition, the patent ensures that even at reduced line widths, the polysilicon gate maintains proper dimensions and shape. This preliminary structuring enables continued high device performance despite smaller feature sizes, allowing increased circuit density without sacrificing reliability.
Solution Approach 2:
The patent changes the processing parameters by introducing a multi-step deposition process with the mandrel as a reference structure. This allows precise control of polysilicon gate thickness and shape parameters, ensuring that device performance parameters remain within acceptable ranges even as line width parameters are reduced to increase circuit density.
3Ease of manufacture
If conventional polysilicon gate processing is used, then ease of manufacture is maintained, but device performance deteriorates at reduced geometries
Solution Approach 1:
The mandrel formation step is designed to be compatible with conventional semiconductor manufacturing processes. By using standard deposition and etching techniques to create the mandrel structure, the patent maintains ease of manufacture while enabling improved device performance at reduced geometries. The additional steps required are minimal and can be integrated into existing process flows.
Solution Approach 2:
The mandrel acts as an intermediary structure that can be formed and removed using conventional process equipment. This intermediary enables precise polysilicon gate formation at reduced geometries without requiring new types of equipment or fundamentally changing the manufacturing approach, thus maintaining ease of manufacture while improving device performance.
Data Source
AI summary
A method for manufacturing a MOS device. The method includes providing a semiconductor substrate. The method forms a gate dielectric layer overlying the semiconductor substrate and a polysilicon gate overlying the gate dielectric layer. The polysilicon gate is characterized by a thickness, a width and a polysilicon footing profile. In a specific embodiment, the method performs a TCAD simulation and determines a response of device performance due to the polysilicon footing profile from the model. The method uses the model to provide a process control window for fabricating the polysilicon gate.