Polysilicon Gate Etch with HBr Linewidth Cure for CD Control
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Solution Overview
Problem
Existing polysilicon gate etch processes are unable to regulate dimension differences between different linewidth structures, leading to inconsistent polysilicon gate morphology and limitations in process integration.
Innovation Solution
A polysilicon gate etch method that includes sequential formation of a gate oxide layer, polysilicon layer, hard mask layer, bottom anti-reflection coating, and photoresist on a silicon substrate, followed by photoetching and specific etch gas injection to narrow the bottom anti-reflection coating and hard mask layer, thereby reducing linewidth differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etch process is used, then etch process is simple, but dimension difference between different linewidth structures cannot be regulated
Solution Approach 1:
The etch process is divided into multiple sequential steps: first etch step (removing BARC), second etch step (etching polysilicon gate), and third etch step (trimming hard mask). Each step uses different etch gases and parameters to achieve specific dimensional control objectives, allowing independent optimization of each etch stage to regulate dimension differences between different linewidth structures.
Solution Approach 2:
Different etch gases (CHF3, CF4, C4F8, O2, Ar) and their combinations are used in different etch steps with varying power, pressure, and gas flow rates. The etch selectivity and rate are controlled by changing gas composition and process parameters, enabling precise regulation of dimensional differences between various linewidth structures while maintaining process control.
2Manufacturing precision
If multiple etch steps are added to regulate dimension, then manufacturing precision improves, but process time increases
Solution Approach 1:
The etch steps are combined in a single etch chamber without breaking vacuum, allowing continuous processing. The first, second, and third etch steps are performed sequentially in the same chamber using different gas compositions, eliminating the need for chamber evacuation and repressurization between steps, thus reducing total process time while maintaining precise dimensional control.
Solution Approach 2:
The etch process maintains continuous useful action by performing all etch steps in sequence within the same vacuum environment. The chamber remains under vacuum throughout the process, with only gas composition and flow rates being changed between steps, ensuring continuous material removal and pattern transfer without interruption or loss of process time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces linewidth differences between polysilicon gate structures, optimizing critical dimensions and improving process integration, which helps in saving development costs and time.
Implementation Method 1
injecting an etch gas into an etch chamber, to remove the bottom anti reflection coating outside a polysilicon gate area by etch
Implementation Method 2
injecting only an HBr gas into the etch chamber at a cure flow rate as an etch gas, to etch the bottom anti reflection coating, so that the anti-reflection coating and the photoresist in the polysilicon gate area are further narrowed
Implementation Method 3
injecting an etch gas into an etch chamber
Data Source
AI summary
The present disclosure discloses a polysilicon gate etch method, wherein base on the property that bombarding a photoresist with a HBr plasma cloud can cause a qualitative change in bonding energy of the photoresist, a linewidth cure step using only HBr is added to a polysilicon gate etch process. An injection flow rate of an HBr gas in the linewidth cure step is adjusted according to the needs of process integration, to reduce a linewidth difference between different polysilicon gate structures, thereby optimizing and quantifying post-etch critical dimensions of the polysilicon gate structures of different sizes. Accordingly, the problem of an unchangeable linewidth difference between different polysilicon gate structures after polysilicon etch in case of current fixed mask and lithography condition may be solved.