Integrated Polysilicon Gate Layout for Reduced Cell Pitch

Solution Overview

Problem

Conventional power semiconductor devices require complex manufacturing processes and additional insulating layers to integrate polysilicon devices, leading to increased cell pitch and inefficiencies.

Innovation Solution

The integration of polysilicon devices is achieved without an inter-polysilicon dielectric layer, with coplanar surfaces and electrical connection through conductive vias, allowing for reduced cell pitch and improved fabrication efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an inter-polysilicon dielectric layer is used to electrically isolate the integrated polysilicon device from the gate connector, then electrical isolation is achieved, but the cell pitch increases and manufacturing complexity increases

Engineering Contradiction:

Improveelectrical isolationVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent removes the inter-polysilicon dielectric layer from the conventional structure, extracting this insulating element to simplify the manufacturing process. The gate connector and integrated polysilicon device are formed as separate polysilicon regions without requiring an additional dielectric layer between them, reducing fabrication steps and cell pitch while maintaining electrical isolation through physical separation and coplanar configuration.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the gate connector and integrated polysilicon device into the same polysilicon layer, forming both structures from a single continuous polysilicon region. This consolidation eliminates the need for separate polysilicon deposition and dielectric layer formation steps, simplifying the manufacturing process while maintaining functional separation through geometric configuration rather than material isolation.

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If an inter-polysilicon dielectric layer is used to electrically isolate the integrated polysilicon device from the gate connector, then electrical isolation is achieved, but the cell pitch increases

Engineering Contradiction:

Improveelectrical isolationVSAvoidcell pitch

Core Design Contradiction:

ReliabilityVSLength of moving object

Solution Approach 1:

The patent removes the inter-polysilicon dielectric layer from the conventional structure, extracting this insulating element to simplify the manufacturing process. The gate connector and integrated polysilicon device are formed as separate polysilicon regions without requiring an additional dielectric layer between them, reducing fabrication steps and cell pitch while maintaining electrical isolation through physical separation and coplanar configuration.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If polysilicon devices are integrated using conventional methods with additional insulating layers, then electrical isolation is ensured, but fabrication efficiency decreases

Engineering Contradiction:

Improveelectrical isolationVSAvoidfabrication efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent merges the gate connector and integrated polysilicon device into the same polysilicon layer, forming both structures from a single continuous polysilicon region. This consolidation eliminates the need for separate polysilicon deposition and dielectric layer formation steps, simplifying the manufacturing process while maintaining functional separation through geometric configuration rather than material isolation.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250254909A1Power semiconductor devices including integrated polysilicon devices

Publication Date: 2025.08.07 WOLFSPEED INC

AI summary

A power semiconductor device includes a semiconductor structure comprising an active region, a plurality of gates that extend in a first direction in or on the active region of the semiconductor structure, at least one integrated polysilicon device in or on the semiconductor structure adjacent the active region, and a gate connector electrically connecting the plurality of gates. The gate connector is in or on the semiconductor structure between the at least one integrated polysilicon device and the plurality of gates. The at least one integrated polysilicon device is electrically isolated from the gate connector devoid of an inter-polysilicon dielectric layer therebetween. Related devices and fabrication methods are also discussed.