Polysilicon Gate Layout for p-Channel LDMOSFET Gate Leakage

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Solution Overview

Problem

In semiconductor devices, particularly p-channel LDMOSFETs, the gate insulating film is prone to damage due to impact ionization caused by electron-hole pairs generated during operation, leading to increased gate leakage current.

Innovation Solution

The semiconductor device incorporates a polysilicon gate with an n-type second portion facing the p-type drift region through the gate insulating film, which reduces impact ionization by creating an n-type inversion layer, thereby minimizing electron trapping and gate insulating film damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a p-channel LDMOSFET is operated normally, then current conduction function is achieved, but impact ionization causes electron-hole pairs that damage the gate insulating film and increase gate leakage current

Engineering Contradiction:
Improvegate insulating film durabilityVSAvoidimpact ionization and electron-hole pair generation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent utilizes the harmful impact ionization effect by positioning a lightly-doped drain region adjacent to the channel, where generated electrons are collected to form a useful current component, thereby converting the harmful ionization into a beneficial current contribution that reduces the need for higher drive currents

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent introduces an n-type layer between the p-type drift region and the n-type buried layer. This intermediary layer manages carrier flow and reduces direct impact on the gate insulating film by providing a controlled path for electron-hole recombination, thereby protecting the gate structure from damage

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If the gate insulating film is exposed to high electric fields during operation, then device functionality is maintained, but the film suffers damage and leakage current increases

Engineering Contradiction:
Improvedevice functionalityVSAvoidgate insulating film damage
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent modifies the doping concentration parameters in the drift region and adjacent areas, creating a graded doping profile that reduces peak electric fields. By changing the doping parameters (concentration, depth, width), the device maintains functionality while reducing the harmful electric field stress on the gate insulating film

Inventive Principle:
Principle #35Parameter changes

3Power

If electron-hole pairs are generated through impact ionization, then current conduction occurs, but electrons get trapped in the gate insulating film causing degradation

Engineering Contradiction:
Improvecurrent conductionVSAvoidgate leakage current
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent converts the harmful trapped electrons into a useful effect by designing the n-type layer to attract and collect these electrons, forming a beneficial accumulation layer that enhances current conduction while preventing electrons from trapping in the gate insulating film, thereby reducing leakage current

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively suppresses gate insulating film damage and reduces gate leakage current by lowering the impact ionization rate and enhancing electron accumulation in the surface layer of the p-type drift region.

Implementation Method 1

an n-type second portion (32) facing at least a portion of the drift region (10) with the gate insulating film (23) interposed therebetween

Methodology Applied
Scientific EffectInversion layer formation: Electric Field

Data Source

PatentUS20240097028A1Semiconductor device and method of manufacturing the same
Publication Date: 2024.03.21 ROHM CO LTD
  • US20240097028A1 patent drawing
  • US20240097028A1 patent drawing
  • US20240097028A1 patent drawing

AI summary

A semiconductor device includes an n-type semiconductor layer, a p-type drift region formed in a surface layer portion of the semiconductor layer, an n-type body region formed in the surface layer portion of the semiconductor layer, a p-type drain region formed in a surface layer portion of the drift region, a p-type source region formed in a surface layer portion of the body region, a gate insulating film formed on a surface of the semiconductor layer, and a polysilicon gate formed on the gate insulating film, wherein a region extending from the source region to a side edge of the drift region is a channel region, and wherein the polysilicon gate includes a p-type first portion facing at least a portion of the channel region, and an n-type second portion facing at least a portion of the drift region.