N-doped and Undoped Polysilicon Gate Morphology Control
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Solution Overview
Problem
In microelectronic technology, the difference in etching rates between N-doped and undoped poly-silicon gates leads to morphological differences after etching, causing potential damage to N-doped poly-silicon gates and affecting semiconductor device performance.
Innovation Solution
A method is introduced where a thicker hard mask layer is formed on N-doped poly-silicon, with the undoped poly-silicon hard mask layer etched to a lesser thickness, and an anti-reflection layer is deposited with different thicknesses to ensure both gates are etched uniformly, thereby reducing morphological differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If N-doped poly-silicon is etched using the same hard mask layer thickness as undoped poly-silicon, then the etching process can be simplified, but the N-doped poly-silicon gate will be over-etched and damaged due to its higher etching rate
Solution Approach 1:
The patent applies different hard mask layer thicknesses to different regions: a first hard mask layer with thickness H1 is formed on N-doped poly-silicon, and a second hard mask layer with thickness H2 is formed on undoped poly-silicon, where H1 > H2. This local differentiation compensates for the higher etching rate of N-doped poly-silicon, preventing over-etching and morphology damage while maintaining process simplicity.
2Productivity
If the etching process continues until undoped poly-silicon is completely etched, then complete gate formation is achieved, but the N-doped poly-silicon gate bottom is damaged creating under-cut
Solution Approach 1:
The patent performs preliminary action by forming a thicker first hard mask layer (thickness H1) on the N-doped poly-silicon before the etching process begins. This preliminary protective layer ensures that when the etching reaches the gate formation completion stage, the N-doped poly-silicon gate bottom is protected from damage and under-cut formation, while still allowing complete gate formation.
3Device complexity
If a uniform hard mask layer is used on both N-doped and undoped poly-silicon, then the manufacturing process is simpler, but morphological differences develop between the two gate types
Solution Approach 1:
The patent implements local quality by creating a multi-layer hard mask structure where the first hard mask layer (thickness H1) is specifically positioned on N-doped poly-silicon and the second hard mask layer (thickness H2) is on undoped poly-silicon. This localized thickness differentiation directly addresses the morphological differences that would otherwise develop, ensuring uniform gate shapes while maintaining reasonable process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces the morphological difference between N-doped and undoped poly-silicon gates after etching, preventing damage and ensuring consistent performance of semiconductor devices.
Implementation Method 1
depositing a hard mask layer on a substrate template having N-doped poly-silicon and undoped poly-silicon
Implementation Method 2
depositing an anti-reflection layer on the N-doped poly-silicon hard mask layer and the undoped poly-silicon hard mask layer
Data Source
AI summary
The present invention discloses a method for reducing the morphological difference between N-doped and undoped poly-silicon gates after etching, comprising the following sequential steps: depositing a hard mask layer on a substrate template having N-doped poly-silicon and undoped poly-silicon to form an N-doped poly-silicon hard mask layer and an undoped poly-silicon hard mask layer respectively, and etching the undoped poly-silicon hard mask layer to make a thickness difference between the N-doped poly-silicon hard mask layer and the undoped poly-silicon hard mask layer; depositing an anti-reflection layer, and etching according to a predetermined pattern until exposing the N-doped poly-silicon, wherein when the N-doped poly-silicon is exposed, the undoped poly-silicon is etched to a certain degree; and removing residuals on the surface of the above formed structure, and etching to form an N-doped poly-silicon gate and an undoped poly-silicon gate, respectively.