Polysilicon Gate Patterning via Two-Print Two-Etch Process
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Solution Overview
Problem
Conventional optical projection lithography struggles to accurately reproduce small feature sizes in semiconductor manufacturing, leading to issues like line end shortening and corner rounding, which can result in device leakage and compromised performance, especially at advanced technology nodes below 45 nm.
Innovation Solution
A two print, two etch (2P2E) process is implemented, using a first mask set to define the location of transistor gate lines and a second mask set to trim the ends of these gates, ensuring a small extension past the active region while maintaining precise control over gate length and spacing, adhering to specific design rules to enhance feature reproduction fidelity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional optical projection lithography is used to pattern transistor gates, then the process is simple and fast, but the critical dimension control deteriorates and line end shortening occurs at advanced technology nodes
Solution Approach 1:
The patent divides the single patterning step into multiple sequential patterning steps (first poly pattern, second poly pattern, mandrel formation, spacer formation). Each step patterns only a portion of the final gate structure, allowing better control over critical dimensions. The segmentation enables precise control of gate width, length, and spacing by independently optimizing each patterning step rather than attempting to pattern all features in a single exposure.
Solution Approach 2:
The patent performs preliminary patterning actions to define mandrels and spacers before forming the final gate structure. The first and second poly patterns are formed in advance to create mandrel structures that guide subsequent spacer formation. This preliminary action ensures that the final gate critical dimensions are determined by well-controlled spacer thickness rather than by direct lithographic patterning, improving CD control at advanced nodes.
2Reliability
If gate extension past active region is increased to prevent line end shortening, then device leakage is reduced, but wafer real estate utilization decreases
Solution Approach 1:
The patent applies different extension lengths to different portions of the gate structure. The first poly pattern extends beyond the active region to prevent line end shortening and ensure reliable electrical communication, while the second poly pattern is trimmed to achieve the desired final gate length. This local differentiation allows the gate to have sufficient extension for reliability while minimizing overall area consumption through precise trimming of excess material.
Solution Approach 2:
The patent changes the lateral dimension parameter of the gate structure through a two-step patterning process. The first poly pattern is formed with a larger lateral dimension that extends past the active region, then the second poly pattern trimming step reduces the lateral dimension to the final desired gate length. This parameter change approach allows optimization of both reliability (through initial extension) and area utilization (through subsequent trimming).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 2P2E process effectively extends transistor gate line ends past the active region, ensuring reliable electrical communication and minimizing line end shortening, while maintaining control over critical dimensions, thus improving device performance and preventing device failure.
Implementation Method 1
An optical projection lithography process can include a patterned mask with a semiconductor circuit layout pattern which is used to image the pattern onto a photosensitive layer, for example photoresist
Data Source
AI summary
A method for designing a mask set including at least one mask includes the implementation of at least one design rule from a set of design rules. The design rules include rules relating to allowable spacing between adjacent features, overlap of features defined by different masks in the mask set, and other characteristics of the mask set.