Polysilicon Gate Planarization via Multi-Step Slurry Segmentation
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Solution Overview
Problem
Existing methods for planarizing polysilicon patterns in semiconductor manufacturing face challenges in achieving uniformity and minimizing damage to surrounding patterns, particularly with large thickness variations in hard mask patterns, which can lead to dishing defects and non-uniform transistor performance.
Innovation Solution
A multi-step process involving the formation of preliminary insulating interlayers with specific polishing and etching techniques using different slurries and dry etching methods to expose and planarize polysilicon and hard mask patterns, ensuring a uniform insulating interlayer and reducing damage to peripheral patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single polishing process is used to planarize the insulating interlayer, then the process is simple and fast, but the surface planarity is poor due to large thickness variations in hard mask patterns
Solution Approach 1:
The polishing process is divided into three distinct stages: first polishing to expose hard mask patterns, second polishing to planarize the insulating interlayer surface, and third polishing to achieve final uniform thickness. This segmentation allows each stage to optimize for its specific goal, resolving the contradiction between simplicity and planarity.
Solution Approach 2:
The first polishing stage performs preliminary action by exposing the hard mask patterns before the final planarization. This preliminary exposure creates the necessary conditions for the second polishing stage to achieve uniform surface planarity across the insulating interlayer.
2Manufacturing precision
If polishing is performed until hard mask patterns are exposed, then the insulating interlayer can be planarized, but damage to surrounding patterns may occur
Solution Approach 1:
Different slurries are used at different stages: a first slurry for initial polishing, a second slurry with different properties for exposing hard mask patterns, and a third slurry for final planarization. Each slurry is optimized for its specific local task, minimizing damage to surrounding patterns while achieving the required planarity.
Solution Approach 2:
The polishing parameters are changed between stages by using different slurries with varying properties. This allows optimization of the polishing rate and surface quality at each stage, reducing harmful effects on surrounding patterns while achieving the necessary insulating interlayer uniformity.
3Manufacturing precision
If the insulating interlayer thickness is reduced to expose hard mask patterns, then the hard mask patterns can be accessed, but the insulating interlayer may become too thin causing dishing defects
Solution Approach 1:
The removal of the insulating interlayer is segmented into multiple polishing stages rather than a single aggressive removal. This allows controlled exposure of hard mask patterns while maintaining sufficient insulating interlayer thickness to prevent dishing defects.
Solution Approach 2:
The first polishing stage performs partial removal to expose hard mask patterns, while subsequent stages perform additional controlled removal. This partial action approach prevents excessive removal that would cause dishing, while still achieving the necessary pattern exposure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process achieves planarized polysilicon and insulating interlayer surfaces despite large hard mask pattern thickness variations, enabling the manufacture of transistors with metal gates and improved performance by minimizing dishing defects and property variations.
Implementation Method 1
a first slurry to polish the first preliminary insulating interlayer to a predetermined thickness
Implementation Method 2
a second slurry is used to polish the first preliminary insulating interlayer until at least one upper surface of the hard mask patterns may be exposed. The second slurry may have a slower polishing rate than the first slurry
Implementation Method 3
etching the second preliminary insulating interlayer may be performed by a dry etching process having a high etch selectivity with respect to the hard mask pattern
Implementation Method 4
The second polishing may be performed using a third slurry having a slower polishing rate for the polysilicon patterns than for the hard mask patterns and the third preliminary insulating interlayer
Data Source
AI summary
Methods of manufacturing a semiconductor device include forming integrated structures of polysilicon patterns and hard mask patterns on a substrate divided into at least an NMOS forming region and a PMOS forming region. A first preliminary insulating interlayer is formed on the integrated structures. A first polishing of the first preliminary insulating interlayer is performed until at least one upper surface of the hard mask patterns is exposed, to form a second preliminary insulating interlayer. The second preliminary insulating interlayer is etched until the upper surfaces of the hard mask patterns are exposed, to form a third preliminary insulating interlayer. A second polishing of the hard mask patterns and the third preliminary insulating interlayer is performed until the polysilicon patterns are exposed to form an insulating interlayer. The polysilicon patterns are removed to form an opening. A metal material is deposed to form a gate electrode pattern in the opening.