Polysilicon Gate Resistance Reduction via Boron Diffusion

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Solution Overview

Problem

The carbon co-implantation process in semiconductor manufacturing suppresses the diffusion of P-type heavily doped boron atoms in polysilicon gates, leading to increased resistance, which complicates the control of semiconductor device manufacturing due to Short Channel Effects.

Innovation Solution

A method that involves depositing a salicide block layer, performing P-type heavily doped boron implantation and thermal annealing before the carbon co-implantation process, and re-depositing salicide layers to ensure sufficient diffusion of boron atoms, thereby reducing polysilicon gate resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If carbon co-implantation process is performed during LDD implantation, then ultra-shallow junctions are formed and SCE is suppressed, but boron atom diffusion in polysilicon gate is reduced and gate resistance increases

Engineering Contradiction:
Improvejunction depth precisionVSAvoidgate resistance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent performs P-type heavily doped boron implantation and thermal annealing treatment before the carbon co-implantation process. This preliminary action allows boron atoms to diffuse into the polysilicon gate and form reservoirs prior to carbon implantation, ensuring sufficient gate doping is achieved before carbon atoms interfere with subsequent boron diffusion during LDD processing.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If channel length is decreased to improve integration density, then manufacturing precision improves, but Short Channel Effects increase and process control becomes more difficult

Engineering Contradiction:
Improvechannel dimension controlVSAvoidprocess control complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent changes the temporal parameter of the carbon implantation process by performing it at a specific stage (after gate doping but before LDD implantation) rather than simultaneously with LDD implantation. This parameter change allows optimization of both ultra-shallow junction formation and polysilicon gate resistance without increasing process control complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively decreases the polysilicon gate resistance by allowing boron atoms to diffuse sufficiently, reducing the resistance from 700 Ω/square to 300 Ω/square in the 55 nm scale process, thereby improving the manufacturing control of semiconductor devices.

Implementation Method 1

the boron atoms in the polysilicon gate can not diffuse sufficiently and the resistance of the P-type polysilicon gate increases

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 2

carbon atoms help to reduce the diffusion of boron atoms in the silicon substrate

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 3

low energy boron ion implantation process is used in Lightly Doped Drain (LDD) process

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Data Source

PatentUS8409975B1Method for decreasing polysilicon gate resistance in a carbon co-implantation process
Publication Date: 2013.04.02 SHANGHAI HUALI MICROELECTRONICS CORP
  • US8409975B1 patent drawing
  • US8409975B1 patent drawing
  • US8409975B1 patent drawing

AI summary

A method for decreasing polysilicon gate resistance in a carbon co-implantation process which includes: depositing a first salicide block layer on a formed gate of a MOS device and etching it to form a first spacer of a side surface of the gate of the MOS device; performing a P-type heavily doped boron implantation process and a thermal annealing treatment, so as to decrease the resistance of the polysilicon gate; removing said first spacer, performing a lightly doped drain process, and performing a carbon co-implantation process at the same time, so as to form ultra-shallow junctions at the interfaces between a substrate and source region and drain region below the gate; re-depositing a second salicide block layer on the gate and etching the mask to form a second spacer; forming a self-aligned silicide on the surface of the MOS device. The invention can decrease the resistance of the P-type polysilicon gate.