Polysilicon Gate Sidewall Angle Control via RF Bias Optimization

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Solution Overview

Problem

The variation in sidewall angle of polysilicon gates from batch to batch in semiconductor device manufacturing leads to significant impacts on parametric Idrive currents and yield, while current methods only control the gate bottom critical dimension, neglecting sidewall angle control.

Innovation Solution

A method involving the selection of optimized RF power and etch time for various etch steps, along with the development of a statistical model correlating sidewall angle with RF bias power and etch time, to predict and control the sidewall angle variation while maintaining bottom critical dimension control performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sidewall angle variation is reduced through process optimization, then yield and parametric performance improve, but process complexity increases

Engineering Contradiction:

Improveyield and parametric performanceVSAvoidprocess complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements feedback by measuring sidewall angle from test structures and using this information to adjust and optimize the etch process parameters. This closed-loop approach enables systematic reduction of sidewall angle variation and improvement of yield while providing a method to control the increasing process complexity through data-driven parameter optimization.

Inventive Principle:

Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces sidewall angle variation from batch to batch, improving yield and parametric performance by optimizing RF power and etch time, and using a statistical model to predict and match target sidewall angles, resulting in more consistent polysilicon gate formation.

Implementation Method 1

a first, second, third, fourth, and fifth plasma process are performed in a plasma reactor

Methodology Applied

Scientific EffectPlasma: Plasma

Implementation Method 2

each of the plurality of plasma process recipes includes an optimized first, second, third, fourth, and fifth radio frequency (RF) power

Methodology Applied

Scientific EffectRadio frequency power:

Implementation Method 3

sidewall angle of a gate and RF bias power and etch time of one or more etch steps

Methodology Applied

Scientific EffectAnisotropic etching:

Data Source

PatentUS8709951B2Implementing state-of-the-art gate transistor, sidewall profile/angle control by tuning gate etch process recipe parameters

Publication Date: 2014.04.29 TEXAS INSTRUMENTS INC

AI summary

In accordance with the invention, there are methods of controlling the sidewall angle of a polysilicon gate from batch to batch while maintaining current bottom critical dimension control performance. The method can include generating a correlation between a sidewall angle of a gate and RF bias power and etch time of one or more etch steps during the formation of the gate, developing a statistical model for the sidewall angle as a function of one or more of polysilicon density, polythickness, and etcher, and predicting a sidewall angle using the statistical model for a given polydensity, a given polythickness, and a given etcher. The method can also include comparing the predicted sidewall angle with a target sidewall angle and determining an optimized RF bias power and optimized etch time of one or more etch steps during the formation of the gate using the correlation to match the target sidewall angle.