Polysilicon Gate Sidewall Oxide for Image Sensor Leakage Control
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Solution Overview
Problem
The existing methods for patterning polysilicon gates in image sensor devices often result in necking or damaged edges, leading to current leakage and white pixels due to the difficulty in achieving uniform sidewall profiles and controlling the etch stop process.
Innovation Solution
A method is developed that includes depositing a gate dielectric layer, a polysilicon layer, and a protection film, followed by an oxide layer formation on the sidewalls through oxygen treatment, which protects the polysilicon layer during the etching process, minimizing surface defects and maintaining a sharp tip profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to pattern polysilicon gates, then the gate structure can be formed, but necking and damaged edges occur leading to current leakage and white pixels
Solution Approach 1:
A protection oxide layer is formed on the polysilicon gate sidewalls before the etching process. This preliminary protective action prevents direct exposure of the gate oxide to damaging etchants and plasma conditions, thereby maintaining sidewall uniformity and preventing necking while preserving gate oxide integrity
Solution Approach 2:
The protection oxide layer acts as an intermediary barrier between the polysilicon gate structure and the etching environment. It absorbs the harmful effects of the etchant and plasma, protecting the underlying gate oxide from damage while allowing the etching process to proceed on the polysilicon and other structures
2Speed
If thinner gate oxides are used to increase Idsat and improve speed, then device speed increases, but reliability under plasma etching and ion implantation conditions deteriorates
Solution Approach 1:
The protection oxide layer is formed on the polysilicon gate sidewalls before plasma etching and ion implantation processes. This preliminary protective measure shields thin gate oxides from direct exposure to plasma and ion bombardment, enabling the use of thinner oxides for high-speed devices without compromising reliability
Solution Approach 2:
The protection oxide layer serves as a cushioning barrier that absorbs and dissipates the energy of incoming ions and plasma particles before they can reach and damage the thin gate oxide. This beforehand cushioning enables thin oxide devices to withstand subsequent plasma and ion processing steps
3Manufacturing precision
If the etch stop process is difficult to control, then manufacturing complexity increases, but achieving uniform sidewall profiles becomes even more difficult
Solution Approach 1:
The sidewall profile control function is extracted from the etch stop process and transferred to the protection oxide layer formation process. By forming the protection oxide with standard deposition techniques rather than relying on precise etch stop control, the manufacturing process becomes simpler while achieving better sidewall uniformity
Solution Approach 2:
The protection oxide layer serves as an intermediary that decouples the sidewall profile formation from the etch stop process. The uniform thickness of the protection oxide, controlled by deposition parameters rather than etch stop, directly determines the sidewall profile, simplifying the overall manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the occurrence of necking and damaged edges, ensuring a defect-free polysilicon gate structure that minimizes current leakage and prevents white pixels by maintaining the integrity of the polysilicon layer and preserving its uniformity.
Implementation Method 1
a sidewall oxide layer is formed over a sidewall of the gate electrode
Data Source
AI summary
An image sensor includes a semiconductor substrate, a gate dielectric layer, a gate electrode, a protection oxide film, and a nitride hard mask. The gate dielectric layer is over the semiconductor substrate. The gate electrode is over the gate dielectric layer. An entirety of a first portion of the gate dielectric layer directly under the gate electrode is of uniform thickness. The protection oxide film is in contact with a top surface of the gate electrode. The gate dielectric layer extends beyond a sidewall of the protection oxide film. The nitride hard mask is in contact with a top surface of the protection oxide film.