Polysilicon Gate Electrode Silicide Break Prevention
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Solution Overview
Problem
Existing semiconductor device fabrication methods fail to prevent breaks in metal silicide films at the PN junction, leading to increased resistance in gate electrodes, which is critical as devices miniaturize, and current solutions either increase interconnect width or do not effectively address the breakage issue.
Innovation Solution
The method involves forming a polycrystalline silicon film with a P-type part and an N-type part on a substrate, where the P-type part is doped with a heavier element than the P-type impurity to reduce the thickness difference and step height between the parts, ensuring the metal silicide film is evenly covered and less likely to break, using ion implantation and specific dopants like indium, arsenic, or gallium to smooth or taper the interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate electrode is made finer to support miniaturization, then the degree of integration increases, but the resistance of the gate electrode increases due to reduced cross-sectional area
Solution Approach 1:
The patent changes the material composition of the gate electrode by forming a silicide layer (e.g., nickel silicide, cobalt silicide) on the polysilicon gate electrode. This material parameter change reduces the gate electrode resistance while maintaining the fine dimensions required for miniaturization, thereby supporting higher integration density without sacrificing electrical performance
2Reliability
If a metal silicide film is formed on a polycrystalline silicon film with a PN junction, then the gate electrode resistance is reduced, but the metal silicide film becomes broken at the PN junction due to silicide agglomeration
Solution Approach 1:
The patent applies local quality by selectively modifying the polysilicon film at the PN junction region through additional impurity doping (e.g., phosphorus or boron) to create a localized region with different electrical properties. This local modification prevents silicide agglomeration at the critical PN junction interface while maintaining the low-resistance silicide film in other regions, thereby preserving both low resistance and film integrity
Solution Approach 2:
The patent performs preliminary action by pre-doping the polysilicon film at the PN junction region with additional impurities before forming the metal silicide layer. This preliminary modification of the substrate prevents the formation of defects and agglomeration during subsequent silicidation processes, ensuring continuous and intact metal silicide film formation across the entire gate electrode including the PN junction region
3Stability of the object's composition
If the width of the gate electrode is increased at the PN junction interface to prevent silicide film breaks, then the metal silicide film integrity is improved, but the interconnect pitch increases
Solution Approach 1:
The patent uses local quality by applying selective impurity doping only at the PN junction region rather than increasing the overall gate electrode width. This localized modification prevents silicide film breaks at the critical interface while maintaining the original interconnect pitch and spacing, thereby achieving film integrity without sacrificing integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents breaks in the metal silicide film at the PN junction, maintaining low resistance in gate electrodes without increasing interconnect width, thus supporting further miniaturization and integration density in semiconductor devices.
Implementation Method 1
the P-type part is further doped with a heavier element than a P-type impurity that determines a conductivity type of the P-type part
Data Source
AI summary
A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a polycrystalline silicon film continuously formed on the substrate to cover the first and second regions and a metal silicide film formed on the polycrystalline silicon film. The polycrystalline silicon film has a P-type part located on the first region and an N-type part coming into contact with the P-type part and located on the second region, and the P-type part is further doped with a heavier element than a P-type impurity that determines a conductivity type of the P-type part.