Polysilicon Gate Strain Introduction via Lattice Expansion
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Solution Overview
Problem
Existing methods for introducing strain into semiconductor channels are complex and may introduce defects, with reduced effectiveness as device feature sizes decrease, necessitating a new method for enhanced strain control in NMOS and PMOS devices.
Innovation Solution
A method involving doping or implanting elements into a polysilicon gate layer, followed by high-temperature annealing to induce strain in the channel, allowing for control of strain direction and magnitude through element selection, dose, and annealing conditions, without additional process complexity or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If global strain structures (SiGe/SiC layers) are used to produce strain in the channel, then carrier mobility is enhanced, but the process becomes complicated and defects may be introduced
Solution Approach 1:
The patent uses a stress liner layer as an intermediary between the substrate and the channel to transfer stress. This stress liner acts as a mediator that generates the desired tensile or compressive strain in the channel without requiring complex SiGe/SiC epitaxial structures, thereby simplifying the manufacturing process while maintaining carrier mobility enhancement
Solution Approach 2:
The patent changes the material composition parameter of the stress liner layer (using different materials like SiN, SiO2, or metal layers with different stress properties) to control the type and magnitude of strain in the channel, allowing flexibility in optimizing carrier mobility without changing the overall device structure
2Reliability
If local strain structures (SiGe in S/D region) are used to produce strain in the channel, then carrier mobility is enhanced, but the process becomes complicated and defects may be introduced
Solution Approach 1:
The stress liner layer serves as an intermediary that distributes stress uniformly across the channel region, eliminating the need for localized SiGe insertion into source/drain regions. This approach simplifies the fabrication process by avoiding complex ion implantation and annealing steps required for local strain structures
3Reliability
If existing strain introduction methods are used, then some strain effect is achieved, but the strain strength is insufficient for tiny sized devices
Solution Approach 1:
The patent optimizes the stress liner layer parameters including material selection, thickness, and stress magnitude to generate sufficiently strong strain in miniaturized devices. By adjusting these parameters, the strain strength can be scaled to match the reduced dimensions of modern transistors, maintaining effective carrier mobility enhancement
Solution Approach 2:
The patent introduces a new dimensional approach by placing the stress source (stress liner) in a different spatial dimension - beneath the channel rather than within or adjacent to the source/drain regions. This allows for more effective strain transmission to the channel in scaled devices
4Reliability
If existing strain introduction methods are used, then some strain effect is achieved, but control over strain level and type is limited
Solution Approach 1:
The patent provides versatile strain control by enabling independent adjustment of multiple parameters: stress liner material composition, thickness, residual stress level, and positioning. These parameter changes allow precise control over both the magnitude and type (tensile/compressive) of strain applied to the channel, adapting to different device requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively introduces stronger, controlled strain into semiconductor channels, enhancing carrier mobility while maintaining process simplicity and flexibility, without introducing defects.
Implementation Method 1
performing annealing such that lattice change occurs in the polysilicon that is doped or implanted with the first element in the high-temperature crystallization process, thereby producing a first strain
Implementation Method 2
introducing the first strain to the channel through the gate dielectric layer to cause a change in the size of the semiconductor lattice in the surface layer of the channel region
Data Source
AI summary
The present invention relates to a method of introducing strain into a channel and a device manufactured by using the method, the method comprising: providing a semiconductor substrate; forming a channel in the semiconductor substrate; forming a first gate dielectric layer on the channel; forming a polysilicon gate layer on the first gate dielectric layer; doping or implanting a first element into the polysilicon gate layer; removing a part of the first gate dielectric layer and polysilicon gate layer to thereby form a first gate structure; forming a source/drain extension region in the channel; forming spacers on both sides of the first gate structure; forming a source/drain in the channel; and performing annealing such that lattice change occurs in the polysilicon that is doped or implanted with the first element in the high-temperature crystallization process, thereby producing a first strain in the polysilicon gate layer, and introducing the first strain through the gate dielectric layer to the channel. This method has greater process flexibility and simple process complexity with no additional process cost.