Polysilicon Gate Stress Engineering for DRAM Transistors
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Solution Overview
Problem
The stress memorization technique (SMT) for forming transistors is challenging when depositing a metal layer or hard mask on a polysilicon layer, limiting its applicability to devices like DRAM, as it complicates the formation of a channel region under tensile or compressive stress.
Innovation Solution
The semiconductor device incorporates polysilicon layers with different elements (germanium and carbon) in NMOS and PMOS transistors to create tensile and compressive stress respectively, enhancing carrier mobility by using specific impurity regions and conductive layers, allowing for improved operation characteristics suitable for various memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the stress memorization technique (SMT) method is used to form a channel region under tensile or compressive stress, then high-speed operation characteristics are improved, but depositing a metal layer pattern or hard mask on the polysilicon layer pattern becomes difficult
Solution Approach 1:
The gate electrode structure is segmented into multiple layers: a lower polysilicon layer and an upper polysilicon layer with different stress characteristics. This segmentation allows each layer to serve different functions - the lower layer provides stress to the channel region for high-speed operation, while the upper layer serves as a platform for depositing metal layer patterns and hard masks, thus resolving the contradiction between achieving high-speed operation and ease of manufacturing subsequent layers.
Solution Approach 2:
The lower polysilicon layer acts as an intermediary between the substrate and the upper polysilicon layer. It transfers stress to the channel region while allowing the upper layer to be used for subsequent processing steps. This intermediary structure enables both the stress application needed for high-speed operation and the ease of manufacturing required for depositing additional layers.
2Speed
If the stress memorization technique (SMT) method is used to change the stress of a channel region, then high-speed operation is achieved, but the method is not applicable to various memory devices such as DRAM
Solution Approach 1:
The gate electrode structure with multiple polysilicon layers is designed to be universal and applicable to various types of semiconductor devices including logic circuits and memory devices such as DRAM. The multi-layer structure provides both stress application capability for high-speed operation and compatibility with subsequent processing steps, making it versatile across different device types.
Solution Approach 2:
The invention changes the structural parameters of the gate electrode from a single layer to multiple layers with different compositions and stress characteristics. This parameter change enables the structure to simultaneously provide stress application for high-speed operation and serve as a foundation for subsequent metal layer and hard mask deposition, thereby expanding adaptability to various memory devices.
3Device complexity
If a single polysilicon layer is used as the gate electrode, then the structure is simple, but it cannot provide both tensile and compressive stress to different channel regions
Solution Approach 1:
Different regions of the gate electrode structure are assigned different qualities - the lower polysilicon layer has different composition and stress characteristics compared to the upper polysilicon layer. This local differentiation allows the lower layer to provide tensile or compressive stress to the channel region for high carrier mobility, while the upper layer maintains structural integrity and facilitates subsequent processing, thus achieving high productivity without excessive complexity.
Solution Approach 2:
The gate electrode is constructed as a composite structure with multiple polysilicon layers having different compositions and stress properties. This composite approach enables the structure to provide both tensile and compressive stress to different channel regions, enhancing carrier mobility and productivity while maintaining manageable structural complexity through systematic design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases carrier mobility and improves operation characteristics of NMOS and PMOS transistors, making them suitable for high-speed, low-voltage applications in memory devices like DRAM, by applying appropriate stress to the channel regions.
Implementation Method 1
a stress memorization technique (SMT) method in which a silicon nitride layer is formed on a substrate and a heat treatment is performed on the substrate is being used to change the stress of a channel region
Implementation Method 2
a stress memorization technique (SMT) method in which a silicon nitride layer is formed on a substrate and a heat treatment is performed on the substrate is being used to change the stress of a channel region
Implementation Method 3
N-type impurity regions may be formed by implanting n-type impurities at first upper portions of the substrate adjacent to the first gate structure
Implementation Method 4
P-type impurity regions may be formed by implanting p-type impurities at second upper portions of the substrate adjacent to the second gate structure
Data Source
AI summary
In semiconductor devices, methods of forming the same, the semiconductor device include a first gate structure having a first gate oxide layer pattern, a first polysilicon layer pattern containing atoms larger than silicon and a first hard mask layer pattern on substrates under tensile stress. N-type impurity regions are formed under the surface of the substrate on both sides of the first gate structure. A second gate structure having a second gate oxide layer pattern, a second polysilicon layer pattern containing atoms smaller than silicon and a second hard mask layer pattern on substrates under compressive stress. Additionally, P-type impurity regions are formed under the surface of the substrate on both sides of the second gate structure. The semiconductor devices have good device properties.