Polysilicon Gate Trench Structure for DRAM Miniaturization
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Solution Overview
Problem
As DRAMs undergo miniaturization and integration, the reduction in trench width affects storage performance due to corresponding decreases in gate and conductive layer widths, necessitating a method to maintain conductivity while reducing trench size.
Innovation Solution
A semiconductor structure manufacturing method involving the sequential stacking of a barrier layer and a conductive polysilicon layer within gate trenches, where the conductive layer's width is equal to the trench width, ensuring conductivity and allowing for reduced trench sizes without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the trench width is reduced for miniaturization, then the integration density is improved, but the conductive layer width decreases and conductivity deteriorates
Solution Approach 1:
The patent changes the material parameter of the conductive layer from traditional metal to polysilicon, which has different electrical properties. Polysilicon maintains adequate conductivity even at reduced widths, allowing the trench to be miniaturized without compromising the conductive path. This material parameter change resolves the contradiction between reduced trench width and maintained conductivity.
Solution Approach 2:
The patent employs a composite structure with multiple layers including the polysilicon conductive layer, barrier layers, and gate dielectric layers. This composite material approach allows optimization of each layer's properties - the polysilicon provides conductivity, the barrier layers prevent diffusion, and the gate dielectric provides insulation - collectively maintaining reliability while enabling miniaturization.
2Quantity of substance
If the gate width is reduced for miniaturization, then the storage capacity is improved, but the storage performance deteriorates
Solution Approach 1:
By changing the conductive layer material to polysilicon and adjusting its doping concentration and thickness parameters, the patent maintains sufficient electrical properties in miniaturized gates. The polysilicon's inherent properties allow reduced gate dimensions while preserving the charge storage capability needed for DRAM operation, thus improving storage capacity without sacrificing performance.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the gate structure. The polysilicon conductive layer is specifically engineered with appropriate doping levels and thickness to provide localized charge storage functionality, while other regions use different materials optimized for their specific functions (barrier layers for diffusion prevention, gate dielectric for insulation). This local optimization enables miniaturization while maintaining overall storage performance.
Data Source
AI summary
The present disclosure provides a manufacturing method and measurement method of a semiconductor structure, and a semiconductor structure, relating to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a base including multiple gate trenches; and forming a gate structure in each of the gate trenches, wherein each gate structure includes a barrier layer and a conductive layer, the barrier layer and the conductive layer are sequentially stacked, the barrier layer is in contact with a bottom wall of each of the gate trenches, and a material of the conductive layers includes polysilicon.