Polysilicon Gate Trimming for Reduced Line End Shortening
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Solution Overview
Problem
Conventional resist trimming processes in semiconductor processing result in high line end shortening (LES) ratios, leading to transistor leakage and compatibility issues with existing processes, particularly in SRAM ICs, due to the use of hard masks which increase costs and complicate defect control.
Innovation Solution
A method involving partial trimming of the resist layer using O2-based chemistry and tailored etch chemistries to achieve a reduced LES ratio, where the etch process forms gate conductors with a polysilicon line feature that maintains the desired dimensions while minimizing line end pullback, using a patterned resist layer and non-chlorine based fluorine-based chemistries to prevent sidewall isotropic etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional resist trimming processes are used to achieve feature sizes smaller than lithographic ground rule, then the critical dimension of polysilicon line can be reduced to target dimension, but the line end shortening ratio becomes excessively high (>1.5 to 2)
Solution Approach 1:
The patent changes the chemical parameters of the etching process by using O2-based chemistry with specific flow rates and power settings. This modifies the etch profile to achieve isotropic etching that uniformly trims both line width and line ends, reducing the LES ratio from >1.5 to approximately 1.0-1.2 while maintaining sub-ground-rule CD dimensions.
Solution Approach 2:
The patent replaces the mechanical/conventional resist trimming approach with a chemically-controlled etching process. Instead of relying on physical mask removal or conventional trimming that causes differential erosion, the process uses plasma chemistry (O2-based) to achieve uniform material removal across the polysilicon structure, eliminating the excessive line end pullback.
2Length of moving object
If hard mask processes are used to reduce LES ratio, then line end shortening can be reduced, but etch selectivity is lost causing erosion of silicon nitride liner in STIs
Solution Approach 1:
The patent applies local quality by using O2-based etch chemistry that exhibits selective reactivity: it etches polysilicon at controlled rates while having minimal impact on silicon nitride liners. The localized chemical interaction allows uniform trimming of polysilicon line ends without eroding the STI isolation structures, maintaining both LES reduction and liner integrity.
Solution Approach 2:
The O2-based etch chemistry acts as an intermediary that enables selective material removal. The plasma chemistry mediates between the polysilicon gate structure and the silicon nitride liner, allowing controlled trimming of the polysilicon while preserving the underlying STI structures through selective etching mechanisms.
3Length of moving object
If hard masks are used to pattern polysilicon gates, then LES ratio can be reduced, but manufacturing cost increases and defect control becomes more difficult
Solution Approach 1:
The patent extracts and eliminates the hard mask step from the manufacturing process. By using O2-based plasma etching with the patterned resist as a direct mask, the process achieves the desired polysilicon trimming without requiring additional hard mask materials, deposition steps, or removal processes, thereby reducing manufacturing complexity and cost.
Solution Approach 2:
The patterned resist layer serves multiple functions: it acts as the primary pattern mask and also provides self-limiting protection during the O2-based etching process. The resist structure itself defines the etch boundaries, eliminating the need for separate hard mask layers and simplifying the overall manufacturing process while maintaining precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the LES ratio to less than 1.5, improving transistor performance and compatibility with existing processes, while maintaining high yield and reducing production costs, as demonstrated by SEM images showing reduced polysilicon line end pullback and compatibility with STI/silicon nitride liner schemes.
Implementation Method 1
partially trimming the resist layer to produce resist dimensions less than desired dimensions
Implementation Method 2
patterning the device layer or layers of the gate conductor using the partially trimmed resist layer as a mask
Data Source
AI summary
A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.