Polysilicon Gettering Layer for SOI Wafer Impurity Control
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Solution Overview
Problem
Current gettering techniques for SOI wafers with thick active layers are inefficient, leading to impurity contamination issues that affect the reliability and durability of semiconductor devices, particularly in critical applications like automotive and aviation, where long-term integrity is crucial.
Innovation Solution
A polysilicon layer is introduced between the active silicon layer and the buried oxide layer to act as a gettering site for metallic impurities, preventing diffusion through the buried oxide and improving gate oxide integrity and reducing leakage currents, while also serving as an anti-stiction layer for micromechanical structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional gettering methods are used in SOI wafers, then manufacturing process is simple, but gettering efficiency is insufficient leading to impurity contamination
Solution Approach 1:
The patent embeds a polysilicon gettering layer within the SOI wafer structure, nesting it between the active silicon layer and the buried oxide layer. This nested configuration allows the gettering function to be integrated into the existing wafer architecture without requiring separate external gettering systems, thereby improving reliability while controlling complexity.
Solution Approach 2:
The polysilicon layer serves as an intermediary element between the active silicon layer and the buried oxide layer. It mediates impurity migration by providing a trapping mechanism that intercepts metallic impurities before they can reach critical regions, thus enhancing gettering efficiency without fundamentally altering the basic SOI structure.
2Reliability
If active layer thickness is increased for sensor applications, then sensitivity and durability improve, but impurity contamination risk increases
Solution Approach 1:
The polysilicon gettering layer is positioned below the active silicon layer to preemptively intercept metallic impurities before they can migrate into thick active regions. This preliminary action occurs during thermal processing steps, where the polysilicon layer actively traps impurities that would otherwise contaminate the sensor elements, thereby protecting durability without limiting active layer thickness.
Solution Approach 2:
The patent applies local quality by placing the polysilicon gettering layer specifically in regions where impurity migration is most problematic, particularly beneath thick active layers used in sensor applications. This localized approach targets impurity contamination at its source without requiring uniform modification across the entire wafer structure.
3Reliability
If polysilicon layer is added for gettering, then impurity removal efficiency improves, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the gettering function with existing manufacturing processes by integrating polysilicon layer formation into standard SOI fabrication sequences. The polysilicon layer is deposited and processed alongside other wafer layers using conventional techniques, combining multiple functions (structural support, electrical isolation, and impurity trapping) into a single integrated layer rather than adding separate gettering equipment or processes.
Solution Approach 2:
The invention utilizes parameter changes in thermal processing conditions to activate the gettering function of the polysilicon layer. By adjusting temperature and time parameters during annealing or oxidation steps, the polysilicon layer's ability to trap impurities is enhanced without requiring fundamental changes to manufacturing equipment or process sequences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the gettering efficiency by maintaining constant impurity diffusion distance and reducing device size, improving the reliability and durability of semiconductor devices by effectively removing impurities and preventing stiction issues in micromechanical structures.
Implementation Method 1
maintaining constant impurity diffusion distance
Implementation Method 2
act as a gettering site for metallic impurities
Implementation Method 3
preventing diffusion through the buried oxide
Data Source
AI summary
It is shown in the invention a method for manufacturing a semiconductor wafer structure with an active layer for impurity removal, which method comprises phases of depositing a first layer on a first wafer surface for providing an active layer, an optional phase of preparation for said first layer for next phase, growing thermal oxide layer on a second wafer, bonding said first and second wafers into a stack, annealing the stack for a crystalline formation in said thermal oxide layer as a second layer, and thinning said first wafer to a pre-determined thickness. The invention concerns also a wafer manufactured according to the method, chip that utilizes such a wafer structure and an electronic device utilizing such a chip.