Polycrystalline Silicon Grain Uniformity via Seed Region Crystallization
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Solution Overview
Problem
Polycrystalline silicon layers used in flat panel displays exhibit non-uniform characteristics due to varying grain size and irregular grain boundary distribution, affecting thin film transistor performance.
Innovation Solution
The Super Grain Silicon (SGS) crystallization technique is used to enhance the crystallinity of a seed region, which then spreads to form a crystallization region with uniform grain size and regular grain boundaries, improving the characteristics of the polycrystalline silicon layer and subsequent thin film transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional crystallization methods (SPC, ELC, MIC, MILC) are used to form polycrystalline silicon layer, then the amorphous silicon layer can be crystallized, but the grain size becomes non-uniform and grain boundaries are irregularly distributed
Solution Approach 1:
The patent divides the crystallization process into two distinct stages: first forming a seed region with controlled grain structure using SGS technique, then allowing lateral crystallization to propagate from this seed region. This segmentation of the crystallization process enables precise control over grain size and grain boundary distribution, resolving the non-uniformity problem caused by conventional single-stage crystallization methods.
Solution Approach 2:
The patent performs preliminary crystallization to form a seed region with specific grain structure before the main crystallization process. By pre-establishing a controlled seed region using SGS technique, the subsequent lateral crystallization can propagate uniform grain structures, ensuring consistent grain size and regular grain boundary distribution throughout the final polycrystalline silicon layer.
2Reliability
If amorphous silicon layer is crystallized using conventional methods, then polycrystalline silicon layer is formed, but threshold voltage and off-characteristics of thin film transistors are non-uniform
Solution Approach 1:
The patent applies different crystallization qualities to different regions: the seed region is crystallized using SGS technique to achieve specific grain structure, while the surrounding region undergoes lateral crystallization to propagate this uniform structure. This local quality approach ensures that the region where thin film transistors are formed has optimized grain characteristics, leading to uniform threshold voltage and off-characteristics.
3Manufacturing precision
If seed region area is increased to 400 μm2 or more using SGS technique, then crystallinity is enhanced and spreads to form uniform crystallization region, but the fabrication process becomes more complex
Solution Approach 1:
The patent introduces a metal catalyst layer as an intermediary to facilitate the SGS crystallization process. The metal catalyst (such as Ni, Pd, Au, or Al) mediates the phase transformation from amorphous to polycrystalline silicon, enabling the formation of the seed region with enhanced crystallinity. This intermediary approach simplifies the overall process by providing a clear mechanism for controlled crystallization without requiring excessively complex fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in polycrystalline silicon layers with improved uniformity and regular grain boundary distribution, leading to enhanced thin film transistor characteristics and performance in flat panel displays.
Implementation Method 1
MIC is a method of using phase transfer induction from amorphous silicon to polysilicon by contacting the amorphous silicon layer with metals, such as Ni, Pd, Au and Al, or implanting such metals into the amorphous silicon layer
Implementation Method 2
ELC is a method of crystallizing a silicon layer by irradiating it with an excimer laser and locally heating it to a high temperature for a very short time
Implementation Method 3
SPC is a method of annealing an amorphous silicon layer for several to several tens of hours at a temperature of about 700° C. or less, which is a transition temperature of glass used as a substrate of a display device employing a thin film transistor
Data Source
AI summary
A polycrystalline silicon layer, a flat panel display using the polycrystalline silicon layer, and methods of fabricating the same are provided. An amorphous silicon layer is formed on a substrate. A first pattern layer, a second pattern layer, and a metal catalyst layer are formed on the amorphous silicon layer. The first pattern layer and the second pattern layer are formed to define a region of at least 400 μm2 within which a metal catalyst of the metal catalyst layer is diffused into the amorphous silicon layer. A seed region is crystallized by the diffused metal catalyst. After a crystallization region is grown from the seed region, a semiconductor layer is formed on the crystallization region, so as to fabricate a thin film transistor with excellent characteristics. Using this, a flat panel display is fabricated.