Polysilicon High-Voltage Gates in HKMG ICs Without CMP Thinning
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Solution Overview
Problem
The integration of high voltage devices into integrated circuits (ICs) with high-κ metal gate (HKMG) technology is limited by the susceptibility of gate metal to chemical mechanical polishing (CMP), leading to thinning and design constraints below 1 μm², which restricts the introduction of high voltage devices.
Innovation Solution
Implementing high voltage devices using polysilicon gates with thick gate oxide and conventional dielectrics, allowing for a replacement gate process that avoids damaging the gate oxide and enables larger gate areas, including areas greater than 1 μm², by etching high-κ dielectrics from polysilicon gate areas without harming the thick oxide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-κ metal gate (HKMG) technology is used to increase functional density, then device integration is improved, but gate metal susceptibility to CMP causes thinning and design constraints below 1 μm²
Solution Approach 1:
The gate structure is segmented into two distinct types: HKMG gates for low voltage logic devices and polysilicon gates for high voltage devices. This segmentation allows each gate type to be optimized independently, with polysilicon gates avoiding CMP processing entirely, thus eliminating the thinning issue while maintaining HKMG benefits for standard logic.
Solution Approach 2:
Different gate structures are applied to different regions of the semiconductor device based on local requirements. High voltage devices receive polysilicon gates with thicker oxide layers, while standard logic devices receive HKMG gates. This local differentiation resolves the contradiction by providing appropriate gate characteristics to each region without compromising overall functional density.
2Area of moving object
If gate area is increased to accommodate high voltage devices, then device performance is improved, but CMP-induced thinning becomes more severe
Solution Approach 1:
Instead of using metal gates for high voltage devices with large gate areas, the invention inverts the approach by using polysilicon gates. This material substitution eliminates the CMP thinning problem entirely, allowing gate areas to be increased without the associated thickness degradation, thus enabling larger gate areas for high voltage devices.
3Reliability
If polysilicon gates with thick oxide are used for high voltage devices, then gate voltage handling capability is improved, but process complexity increases due to selective etching requirements
Solution Approach 1:
A sacrificial oxide layer is introduced as an intermediary element in the gate formation process. This sacrificial oxide enables selective removal of high-κ dielectric material from polysilicon gate regions while protecting the polysilicon gate oxide. The intermediary layer simplifies the selective etching process and makes the dual-gate approach more manufacturable.
Data Source
AI summary
An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-κ dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-κ) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one μm2. Polysilicon gates with these adaptations may be operative with gate voltages of 10 V or higher and may be used in embedded memory devices.