Polysilicon Inter-Tier Connections for MEMS- CMOS Parasitic Capacitance Reduction

Solution Overview

Problem

Micro-electromechanical system (MEMS) devices in system-in-packages (SIPs) face issues with large form factor and increased cost due to wire bond connections, which also introduce parasitic capacitance, degrading signal quality.

Innovation Solution

The use of polysilicon inter-tier connections to electrically couple MEMS substrates to CMOS substrates, reducing parasitic capacitance and form factor by providing a short connection distance and minimizing stress on the MEMS substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wire bond connections are used to connect MEMS substrates to CMOS substrates, then electrical connection is achieved, but parasitic capacitance increases and form factor enlarges

Engineering Contradiction:

Improvesignal qualityVSAvoidparasitic capacitance

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the harmful wire bond connection from the system and replaces it with a polysilicon inter-tier connection integrated directly into the substrate structure. This removal of the external wire bond eliminates the source of parasitic capacitance while maintaining the electrical connection function through the integrated polysilicon structure.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the electrical connection function with the substrate structure by integrating polysilicon inter-tier connections directly into the MEMS and CMOS substrates. This consolidation eliminates the need for separate wire bond connections and reduces the overall form factor while minimizing parasitic capacitance through the integrated design.

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If wire bond connections are used to connect MEMS substrates to CMOS substrates, then electrical connection is achieved, but device form factor increases

Engineering Contradiction:

Improveelectrical connectionVSAvoidform factor

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the electrical connection function with the substrate structure by integrating polysilicon inter-tier connections directly into the MEMS and CMOS substrates. This consolidation eliminates the need for separate wire bond connections and reduces the overall form factor while minimizing parasitic capacitance through the integrated design.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from a three-dimensional wire bond connection extending outside the substrate to a planar polysilicon inter-tier connection integrated within the substrate layers. This dimensional change from external vertical bonding to internal planar integration significantly reduces the form factor and footprint of the device.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Reliability

If wire bond connections are used, then electrical connection is achieved, but manufacturing cost increases

Engineering Contradiction:

Improveelectrical connectionVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the electrical connection function with the substrate structure by integrating polysilicon inter-tier connections directly into the MEMS and CMOS substrates. This consolidation eliminates the need for separate wire bond connections and reduces the overall form factor while minimizing parasitic capacitance through the integrated design.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The polysilicon inter-tier connection structure serves multiple functions: it provides electrical connection between substrates, acts as a stress-minimizing interface, and integrates seamlessly with the existing substrate fabrication process. This multi-functionality eliminates the need for separate wire bond materials and processes, reducing manufacturing complexity and cost.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11407636B2Inter-poly connection for parasitic capacitor and die size improvement

Publication Date: 2022.08.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure, in some embodiments, relates to a method of forming a micro-electromechanical system (MEMS) package. The method includes forming one or more depressions within a capping substrate. A back-side of a MEMS substrate is bonded to the capping substrate after forming the one or more depressions, so that the one or more depressions define one or more cavities between the capping substrate and the MEMS substrate. A front-side of the MEMS substrate is selectively etched to form one or more trenches extending through the MEMS substrate, and one or more polysilicon vias are formed within the one or more trenches. A conductive bonding structure is formed on the front-side of the MEMS substrate at a location contacting the one or more polysilicon vias. The MEMS substrate is bonded to a CMOS substrate having one or more semiconductor devices by way of the conductive bonding structure.