Polycrystalline Silicon Layer Deposition for SOI Wafer Manufacturing
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Solution Overview
Problem
Conventional methods for forming a carrier trap layer in SOI wafers face challenges as the polycrystalline silicon layer undergoes single-crystallization during heat treatment, reducing its effectiveness, and existing solutions do not adequately prevent this single-crystallization.
Innovation Solution
A method involving the deposition of a polycrystalline silicon layer on a silicon single crystal base wafer with a previously formed oxide film, using wet cleaning to create a thin oxide film and controlling the deposition temperature between 900°C and 1010°C to suppress single-crystallization and grain growth, along with a heat treatment in a non-oxidizing atmosphere to enhance the carrier trap layer effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polycrystalline silicon layer is deposited to form a carrier trap layer, then the carrier trap effect is improved, but single-crystallization occurs during heat treatment which reduces the carrier trap effect
Solution Approach 1:
The patent applies preliminary anti-action by depositing the polycrystalline silicon layer at a controlled temperature (900-1010°C) and forming a specific interface structure before heat treatment to prevent single-crystallization from occurring during subsequent high-temperature processing. This pre-established structure resists the thermodynamic drive toward single-crystallization that would otherwise occur during standard SOI wafer manufacturing heat treatments.
Solution Approach 2:
The patent changes the deposition temperature parameter to a specific range (900-1010°C) to optimize the formation of the polycrystalline silicon layer. This parameter change ensures that the layer maintains its polycrystalline structure during subsequent heat treatments, thereby preserving the carrier trap effect while allowing standard manufacturing processes to proceed.
2Productivity
If heat treatment is performed to manufacture SOI wafer or device, then the manufacturing process is completed, but the polycrystalline silicon layer undergoes single-crystallization which reduces carrier trap effectiveness
Solution Approach 1:
The patent performs preliminary action by establishing a stable polycrystalline silicon layer structure before the heat treatment steps required for SOI wafer manufacturing. The layer is deposited with specific parameters that create a thermally stable structure, allowing subsequent heat treatments to proceed without causing single-crystallization and loss of carrier trap effectiveness.
3Manufacturing precision
If deposition temperature is increased to improve layer quality, then the layer formation is enhanced, but single-crystallization is promoted during subsequent heat treatment
Solution Approach 1:
The patent optimizes the deposition temperature to a specific range (900-1010°C) that balances layer quality formation with prevention of single-crystallization. This parameter change ensures sufficient layer quality while maintaining polycrystalline structure stability during subsequent heat treatments, resolving the contradiction between formation quality and structural stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses single-crystallization and grain growth, maintaining the carrier trap layer's effectiveness even at high heat treatment temperatures, thereby improving the performance of SOI wafers for higher frequency applications.
Implementation Method 1
it is possible to suppress single-crystallization due to a heat treatment of a step for manufacturing an SOI wafer or a heat treatment of a step for manufacturing a device after deposition by previously forming an oxide film between the surface of a silicon single crystal of a base wafer and a polycrystalline silicon layer to be deposited
Implementation Method 2
forming a high-resistance polycrystalline silicon layer on a base wafer to recombine carriers generated in a high-resistance wafer
Implementation Method 3
a heat treatment in a non-oxidizing atmosphere to enhance the carrier trap layer effect
Data Source
Figure 1
Figure 2(a)~2(i)
Figure 3
AI summary
The present invention is a method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer, each composed of a silicon single crystal, via an insulator film, including the steps of: depositing a polycrystalline silicon layer on the bonding surface side of the base wafer, polishing a surface of the polycrystalline silicon layer, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film, and thinning the bonded bond wafer to form an SOI layer; wherein, as the base wafer, a silicon single crystal wafer having a resistivity of 100 Ω·cm or more is used, the step for depositing the polycrystalline silicon layer further includes a stage for previously forming an oxide film on the surface of the base wafer on which the polycrystalline silicon layer is deposited, and the polycrystalline silicon layer is deposited at a temperature of 900°C or more. As a result, it is possible to provide the method for manufacturing a bonded SOI wafer which can deposit a polycrystalline silicon layer not to promote single-crystallization even though being subjected to a heat treatment step in a step for manufacturing an SOI wafer or a heat treatment step in a step for manufacturing a device.