Polysilicon Removal in Memory Word-Line Contact Regions to Prevent Bridging
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Solution Overview
Problem
The challenge in non-volatile memory devices, such as flash memory, is the difficulty in selectively removing excess material between tightly packed polysilicon lines in the strap regions, leading to residue that can cause bridging and electrical shorts.
Innovation Solution
A patterning process involving photolithography and etching operations is employed to remove excess material between polysilicon lines, using a hard mask stack of oxide and nitride layers, followed by selective etching to create controlled spacings and reduce residue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If photolithography and etching operations are used to remove excess material between polysilicon lines, then residue is reduced or eliminated preventing bridging and electrical shorts, but the process complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the patterning process into multiple distinct operations: forming a first mandrel pattern, depositing a first hard mask layer, forming a second mandrel pattern, depositing a second hard mask layer, and performing selective etching. This segmentation allows each step to be optimized independently, achieving complete material removal without bridging while maintaining controllable process complexity through systematic breakdown of the manufacturing sequence.
2Area of stationary object
If tighter spacing between polysilicon lines is implemented to increase device density, then the area occupied by polysilicon lines is reduced, but the difficulty of removing excess material and preventing residue increases
Solution Approach 1:
The patent introduces vertical dimensionality through multiple deposited layers (first and second hard mask layers with different etch selectivities) and sequential mandrel formation. This multi-layer approach enables precise control of lateral spacing between polysilicon lines by controlling vertical layer thicknesses, achieving the required manufacturing precision for tight spacing through three-dimensional process control rather than relying solely on two-dimensional photolithography resolution.
3Reliability
If multiple etching steps with different selectivities are used to achieve complete material removal, then residue is eliminated preventing electrical shorts, but the manufacturing time and process duration increase
Solution Approach 1:
The patent changes the etching parameters by employing at least two different etching processes with different selectivities: a first etching process that selectively removes the first hard mask layer while preserving the second hard mask layer, and a second etching process that selectively removes the second hard mask layer to expose the polysilicon lines. This parameter variation enables complete material removal and electrical isolation while optimizing the manufacturing cycle time through selective etching rather than requiring complete removal in a single lengthy process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process effectively reduces or eliminates residue, preventing bridging and electrical shorts by ensuring adequate spacing between polysilicon lines, thereby enhancing the reliability and performance of memory devices.
Implementation Method 1
A patterning process involving photolithography and etching operations is employed to remove excess material between polysilicon lines
Implementation Method 2
A patterning process involving photolithography and etching operations is employed to remove excess material between polysilicon lines
Data Source
AI summary
The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.