Polysilicon Inter-Tier MEMS Connection for Low-Parasitic Packaging
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Solution Overview
Problem
Wire bond connections in system-in-packages (SIPs) for MEMS devices result in large form factor, increased cost, and parasitic capacitance, degrading signal quality and performance.
Innovation Solution
Employing polysilicon inter-tier connections to electrically couple MEMS substrates to CMOS substrates, reducing parasitic capacitance and form factor by using conductive polysilicon vias that extend through the MEMS substrate to a bonding structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bond connections are used to electrically couple MEMS substrates to CMOS substrates, then electrical connection is achieved, but parasitic capacitance increases and signal quality degrades
Solution Approach 1:
The patent extracts the harmful wire bond connection from the electrical coupling path between MEMS and CMOS substrates. By removing the wire bond and replacing it with a direct polysilicon inter-tier connection, the parasitic capacitance introduced by the wire bond is eliminated, thereby improving signal quality for capacitive MEMS devices
Solution Approach 2:
The patent changes the electrical connection parameter from wire bond (with high parasitic capacitance) to polysilicon inter-tier connection (with low parasitic capacitance). This parameter change directly reduces the harmful parasitic capacitance while maintaining electrical connectivity, resolving the contradiction between achieving electrical connection and minimizing parasitic effects
2Reliability
If wire bond connections are used for electrical coupling, then electrical connection is established, but the package form factor increases
Solution Approach 1:
The patent merges the electrical connection function with the substrate stacking structure by implementing polysilicon inter-tier connections directly between stacked MEMS and CMOS substrates. This eliminates the need for separate wire bond connections, thereby reducing the package form factor while maintaining reliable electrical connection
Solution Approach 2:
The patent transitions from a planar wire bond connection approach to a vertical inter-tier connection approach by stacking substrates and using polysilicon connections in the vertical dimension. This dimensional change allows electrical connection without increasing the lateral package footprint, thus reducing overall form factor
3Reliability
If wire bond connections are implemented, then electrical coupling is achieved, but manufacturing cost increases
Solution Approach 1:
The polysilicon inter-tier connection structure serves multiple functions: it provides electrical coupling between substrates, acts as a mechanical support structure, and enables vertical stacking integration. This multi-functionality eliminates the need for separate wire bond manufacturing processes, thereby reducing manufacturing cost while maintaining reliable electrical coupling
Data Source
AI summary
The present disclosure relates to a micro-electromechanical system (MEMS) structure including one or more semiconductor devices arranged on or within a first substrate and a MEMS substrate having an ambulatory element. The MEMS substrate is connected to the first substrate by a conductive bonding structure. A capping substrate is arranged on the MEMs substrate. The capping substrate includes a semiconductor material that is separated from the first substrate by the MEMS substrate. One or more conductive polysilicon vias include a polysilicon material that continuously extends from the conductive bonding structure, completely through the MEMS substrate, and to within the capping substrate. The semiconductor material of the capping substrate covers opposing sidewalls of the polysilicon material and an upper surface of the polysilicon material that is between the opposing sidewalls.