Polysilicon MEMS Substrate for Precise Device-Layer Thickness Control
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Solution Overview
Problem
Existing semiconductor substrates, particularly silicon-on-insulator (SOI) wafers, face challenges in precisely controlling the thickness and resistivity of thin silicon layers, leading to suboptimal electrical performance and high manufacturing costs, with time-consuming processes.
Innovation Solution
The development of semiconductor substrates featuring a polysilicon layer with precise thickness and resistivity control, achieved through a method involving etching cavities in a first wafer, depositing and polishing a polysilicon layer, and bonding it with a core substrate to form a MEMS device layer, eliminating the need for SOI wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an SOI wafer is used as substrate for MEMS devices, then the thin silicon layer can be processed to constitute movable parts, but it is difficult to precisely control the thickness of the thin silicon layer, which negatively affects electrical performance
Solution Approach 1:
The patent changes the material parameter from single-crystal silicon to polysilicon, and controls the thickness parameter through deposition process rather than mechanical thinning. The polysilicon layer thickness is precisely controlled during deposition to be within 5-20 micrometers, achieving both precise thickness control and consistent electrical properties across the wafer.
Solution Approach 2:
Instead of using expensive SOI wafers with precisely engineered thin silicon layers, the patent creates a cost-effective alternative by depositing polysilicon layers that replicate the functional requirements. The polysilicon device layer copies the essential characteristics needed for MEMS movable parts while achieving better thickness uniformity and electrical performance.
2Reliability
If an SOI wafer is used as substrate, then the thin silicon layer can be processed to constitute movable parts, but the manufacturing process is time-consuming and costly
Solution Approach 1:
The patent replaces expensive SOI wafers with a more economical substrate structure using standard silicon wafers and deposited polysilicon layers. This substitution significantly reduces material costs and simplifies the fabrication process, making MEMS production more economically viable while maintaining device performance.
Solution Approach 2:
The patent changes the fabrication approach from mechanical thinning and bonding of SOI wafers to direct polysilicon deposition. This parameter change in the manufacturing process reduces the number of steps required, decreases fabrication time, and lowers overall production costs while achieving precise thickness control.
3Manufacturing precision
If a bonded wafer with thinned device wafer is used, then the thinned device wafer can be processed to constitute movable parts, but it is difficult to precisely control the thickness of the thinned device wafer
Solution Approach 1:
The patent replaces the mechanical thinning process (grinding) with a deposition-based approach. Instead of mechanically removing material to achieve desired thickness, the polysilicon layer is deposited to the precise thickness required. This substitution eliminates the complexity of mechanical thinning and bonding processes while achieving superior thickness control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved device performance, reduced fabrication time and cost, and enhanced flexibility, while providing better mechanical and electrical properties for MEMS devices.
Implementation Method 1
a first surface of the first wafer is etched to form a plurality of cavities
Implementation Method 2
depositing a polysilicon layer on the first insulating layer and the core substrate
Implementation Method 3
the polysilicon layer is bonded with the first wafer to cover the plurality of cavities
Data Source
AI summary
A method of fabricating a semiconductor substrate includes the following steps. A first wafer is provided and a first surface of the first wafer is etched to form a plurality of cavities. A second wafer is formed on the first surface, where forming the second wafer includes the following steps: providing a core substrate; forming a first insulating layer on the core substrate; and depositing a polysilicon layer on the first insulating layer and the core substrate. In addition, the polysilicon layer is bonded with the first wafer to cover the cavities, where the polysilicon layer is disposed between the first insulating layer and the first wafer. In addition, a semiconductor substrate and MEMS devices using the semiconductor substrate are also provided.